GitLab

- mtmips: network stability fixes for gardena-smart-gateway
- mtmips: enable CONFIG_USE_PREBOOT and CONFIG_CMD_WDT

Enable CONFIG_USE_PREBOOT on for the gardena mt7688 platforms, so that
this feature can be used here.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

With commit 06985289 ("watchdog: Implement generic watchdog_reset()
version") the init sequence has changed in arch_misc_init(), resulting
in a re-appearance of the d-cache issue on MT7688 boards (e.g. gardena).
When this happens, the first (or sometimes later ones as well) TFTP
command hangs and does not complete correctly. This leads to the
assumption that the d-cache is not in a clean state once the ethernet
driver is called (d-cache is used here for the buffers). The old work-
around with the cache flush somehow does not work any more now with
the new code change.

To fix this issue, this patch now removes the old workaround and selects
CONFIG_SYS_MALLOC_CLEAR_ON_INIT for ARCH_MTMIPS. With this option the
complete malloc area is initialized with zeros (cache lines are touched).
Testing has shown that this also fixes the issue on the MT7688 boards.
Signed-off-by: Stefan Roese <sr@denx.de>
Suggested-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

This patch enables the "wdt" command, which is quite useful for watchdog
testing.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

- Add various STM32MP1 fixes for serial, env, clk, board, i2c ...

- Add STM32MP1 DDR driver update:
	These update introduce the DDR interactive mode described in:
	https://wiki.st.com/stm32mpu/index.php/U-Boot_SPL:_DDR_interactive_mode

	This mode is used by the CubeMX: DDR tuning tool.
	https://wiki.st.com/stm32mpu/index.php/STM32CubeMX

	The DDR interactive mode is NOT activated by default because
	it increase the SPL size and slow down the boot time
	(200ms wait added).

- Enable DM for SATA, SDHC, USB in T2080QDS

- Import Angelo's series to add basic DT support to m68k

Signed-off-by: Angelo Dureghello <angelo@sysam.it>

Changes for v5:
- new patch

This patches move dspi bus-related operations into more
proper location, to avoid the driver to declares them as externs.
Signed-off-by: Angelo Dureghello <angelo@sysam.it>

Add SUPPORT_OF_CONTROL at this stage, to avoid to break build
bisectability.
Signed-off-by: Angelo Dureghello <angelo@sysam.it>

This patch removes CONFIG_SYS_DSPI_XX options from
include/configs "m68k" .h board files, since CTAR
registers are now set with default values in the cf_spi
driver initialization, and configurable by devicetree.

Note, these options cannot be totally removed from the
whitelist, since still used from boards using fsl_dspi.c
(mostly arm-based boards).
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Angelo Dureghello <angelo@sysam.it>

This patch adds devicetree support to the mcfuart.c driver
and removes non DM code.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Angelo Dureghello <angelo@sysam.it>

This patch adds CONFIG_DM_SPI for all m68k boards using
the cf_spi.c driver (DSPI module).
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Angelo Dureghello <angelo@sysam.it>

Converting to driver model and removes non-dm code.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Angelo Dureghello <angelo@sysam.it>

This patch adds cf_spi DM Kconfig option.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Angelo Dureghello <angelo@sysam.it>

Enable DT usage for all m68k boards. To provide a
working single binary, the dts has been kept as embedded.
Signed-off-by: Angelo Dureghello <angelo@sysam.it>

Growing of binary size asks for long assembly jumps.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Angelo Dureghello <angelo@sysam.it>

This patch adds basic dts files for all the m68k boards.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
[trini: Add CONFIG_TARGET_M5329EVB dtbs and update M5329EVB defconfigs]
Signed-off-by: Tom Rini <trini@konsulko.com>

This patch adds fdt support to the m68k architecture.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Angelo Dureghello <angelo@sysam.it>

This patch adds a basic group of devicetrees, one for each
cpu family, including actually just uart and dspi devices,
since these are the drivers supporting devicetree (support
added in this patch-set).
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>

Enable eSDHC, SATA and USB DM for T2080QDS in uboot
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

This patch is to support Freescale sata driver with dts initialized.
Also resolved the following problems.

===================== WARNING ======================
This board does not use CONFIG_DM_SCSI. Please update
the storage controller to use CONFIG_DM_SCSI before the v2019.07 release.
Failure to update by the deadline may result in board removal.
See doc/driver-model/MIGRATION.txt for more info.
====================================================
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

adopt 32 bit addr in fsl_esdhc for CONFIG_PPC.
So  adopt 32 bit address for CONFIG_PPC.
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

Add command tuning for DDR interactive mode, used during
board bring-up or with CubeMX DDR tools to execute software
tuning for the DDR configuration:
- software read DQS Gating (replace the built-in one)
- Bit de-skew
- Eye Training or DQS training
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

Add command tests for DDR interactive mode, used during
board bring-up or with CubeMX DDR tools to verify the
DDR configuration.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

This debug mode is used by CubeMX DDR tuning tools
or manualy for tests during board bring-up.
It is simple console used to change DDR parameters and check
initialization.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

Manage power supply configuration for board using stpmic1
with LPDDR2 or with LPDDR3:
+ VDD_DDR1 = 1.8V with BUCK3 (bypass if possible)
+ VDD_DDR2 = 1.2V with BUCK2
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

Force alignment of the size of parameters array with
the expected value in the binding, that allows compilation
error when the array size change.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

Update DDR configuration with the latest update:

- PUBL_regs: DXnGCR[0]= according to ddr_width to disable Byte
                        lane 2/3 in 16bit
- fix LPDDR2/3 timing_calc to step RL/WL in relaxed
  timings mode
- remove  LPDDR3 RL3 (optional) support vs  MR0[7]
  because MR0[7] can't be read instead  always apply
  worse RL/WL for LPDDR3 when freq < 166MHz)
- change  MR3 to 48ohm drive  for LPDDR2/3
- change default ZPROG[7:4] = 0x1 for LPDDR2/3 ,
  '0' is not allowed even when ODT not used
- use DQSTRN for LPDDR2/3 (it was not set in PIR)
- LPDDR3: set dqsge/dwsgx gate extension to 2,2
  like LPDDR2
-DDRCTRL.dfitmg0:
  + for LPDDR3 tphy_wrlat = WL (as LPDDR2)
  + improvement for relaxed mode vs  RL/Wl at corner case.
    For example @533MHz RL/WL (relaxed) = 9/5 for LPDDR2/3
    and correction to MR2 accordingly
- DDR_PCFGQOS1_1: port1 timeout relaxed from 0x00 to 0x40,
  for LTDC.
- DDR_PCFGWQOS0_0: change vpr level from
  11 to 12 in order to include the CPU on
  the variable priority queue.
- DDR_SCHED: fix to consider 13 levels  (13 levels - 1 = 0xC)
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

Allow fractional support in DDR tools.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

Component Notification DDR controller errata (3.00a):9001313030
Synchronization Time Waited After De-assertion of presetn is
128 pclk Cycles.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

Regression introduced by rebase, when loop
was replaced by readl_poll_timeout() function.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

For STM32MP, the watchdog is based on DM and the function watchod_reset
call the function uclass_get_device(UCLASS_WDT) to found the driver
associated IWDG2.

As this reset is not mandatory in debug putc (the  uart fifo will be
empty after some us), we can simplify the code by removing this call.

And this patch avoid issue when putc is called before initialization
of DM core, before the parsing of the device tree parsing and each
node bound to driver; that also avoid memory leak.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

Remove the trace indicating the end of the DEBUG initialization
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

Solve compilation issue when cli_simple.o is used in SPL
and CONFIG_SPL_ENV_SUPPORT is not defined.

env/built-in.o:(.data.env_htab+0xc): undefined reference to `env_flags_validate'
u-boot/scripts/Makefile.spl:384: recipe for target 'spl/u-boot-spl' failed
make[2]: *** [spl/u-boot-spl] Error 1
u-boot/Makefile:1649: recipe for target 'spl/u-boot-spl' failed
make[1]: *** [spl/u-boot-spl] Error 2
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

Add the DDRPHYC support for clk_set_rate, used in DDR interactive mode
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>