Commit 00f792e0 authored by Heiko Schocher's avatar Heiko Schocher

i2c, fsl_i2c: switch to new multibus/multiadapter support

- added to fsl_i2c driver new multibus/multiadpater support
- adapted all config files, which uses this driver
Signed-off-by: Heiko Schocher's avatarHeiko Schocher <hs@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>
parent ea818dbb
......@@ -1968,6 +1968,18 @@ CBFS (Coreboot Filesystem) support
CONFIG_SYS_I2C_SOFT_SPEED_4 and CONFIG_SYS_I2C_SOFT_SLAVE_4
for defining speed and slave address
- drivers/i2c/fsl_i2c.c:
- activate i2c driver with CONFIG_SYS_I2C_FSL
define CONFIG_SYS_FSL_I2C_OFFSET for setting the register
offset CONFIG_SYS_FSL_I2C_SPEED for the i2c speed and
CONFIG_SYS_FSL_I2C_SLAVE for the slave addr of the first
bus.
- If your board supports a second fsl i2c bus, define
CONFIG_SYS_FSL_I2C2_OFFSET for the register offset
CONFIG_SYS_FSL_I2C2_SPEED for the speed and
CONFIG_SYS_FSL_I2C2_SLAVE for the slave address of the
second bus.
additional defines:
CONFIG_SYS_NUM_I2C_BUSES
......@@ -2213,11 +2225,6 @@ CBFS (Coreboot Filesystem) support
If not defined, then U-Boot uses predefined value for
specified DTT device.
CONFIG_FSL_I2C
Define this option if you want to use Freescale's I2C driver in
drivers/i2c/fsl_i2c.c.
CONFIG_I2C_MUX
Define this option if you have I2C devices reached over 1 .. n
......
......@@ -105,7 +105,7 @@ void cpu_init_f(void)
out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
#endif
#ifdef CONFIG_FSL_I2C
#ifdef CONFIG_SYS_I2C_FSL
out_8(&gpio->par_i2c, GPIO_PAR_I2C_SCL_SCL | GPIO_PAR_I2C_SDA_SDA);
#endif
......
......@@ -134,7 +134,7 @@ int get_clocks(void)
gd->bus_clk = gd->arch.flb_clk;
}
#ifdef CONFIG_FSL_I2C
#ifdef CONFIG_SYS_I2C_FSL
gd->arch.i2c1_clk = gd->bus_clk;
#endif
......
......@@ -115,7 +115,7 @@ void cpu_init_f(void)
out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK);
#endif
#ifdef CONFIG_FSL_I2C
#ifdef CONFIG_SYS_I2C_FSL
CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
#endif
......
......@@ -47,7 +47,7 @@ int get_clocks(void)
gd->bus_clk = CONFIG_SYS_CLK;
gd->cpu_clk = (gd->bus_clk * 2);
#ifdef CONFIG_FSL_I2C
#ifdef CONFIG_SYS_I2C_FSL
gd->arch.i2c1_clk = gd->bus_clk;
#endif
......
......@@ -228,7 +228,7 @@ void cpu_init_f(void)
/* FlexBus Chipselect */
init_fbcs();
#ifdef CONFIG_FSL_I2C
#ifdef CONFIG_SYS_I2C_FSL
CONFIG_SYS_I2C_PINMUX_REG =
CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR;
CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
......@@ -498,7 +498,7 @@ void cpu_init_f(void)
init_fbcs();
#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
#ifdef CONFIG_FSL_I2C
#ifdef CONFIG_SYS_I2C_FSL
CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
#endif
......
......@@ -90,9 +90,9 @@ int get_clocks (void)
gd->bus_clk = gd->cpu_clk;
#endif
#ifdef CONFIG_FSL_I2C
#ifdef CONFIG_SYS_I2C_FSL
gd->arch.i2c1_clk = gd->bus_clk;
#ifdef CONFIG_SYS_I2C2_OFFSET
#ifdef CONFIG_SYS_I2C2_FSL_OFFSET
gd->arch.i2c2_clk = gd->bus_clk;
#endif
#endif
......
......@@ -98,7 +98,7 @@ void cpu_init_f(void)
out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
#endif
#ifdef CONFIG_FSL_I2C
#ifdef CONFIG_SYS_I2C_FSL
out_8(&gpio->par_feci2c,
GPIO_PAR_FECI2C_SDA_SDA | GPIO_PAR_FECI2C_SCL_SCL);
#endif
......@@ -292,7 +292,7 @@ void cpu_init_f(void)
out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
#endif
#ifdef CONFIG_FSL_I2C
#ifdef CONFIG_SYS_I2C_FSL
out_8(&gpio->par_feci2c,
GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
#endif
......
......@@ -270,7 +270,7 @@ int get_clocks(void)
gd->bus_clk = clock_pll(CONFIG_SYS_CLK / 1000, 0) * 1000;
gd->cpu_clk = (gd->bus_clk * 3);
#ifdef CONFIG_FSL_I2C
#ifdef CONFIG_SYS_I2C_FSL
gd->arch.i2c1_clk = gd->bus_clk;
#endif
......
......@@ -212,7 +212,7 @@ void cpu_init_f(void)
GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
#ifdef CONFIG_FSL_I2C
#ifdef CONFIG_SYS_FSL_I2C
out_be16(&gpio->par_feci2c,
GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
#endif
......
......@@ -273,7 +273,7 @@ void setup_5445x_clocks(void)
#endif
}
#ifdef CONFIG_FSL_I2C
#ifdef CONFIG_SYS_I2C_FSL
gd->arch.i2c1_clk = gd->bus_clk;
#endif
}
......@@ -289,7 +289,7 @@ int get_clocks(void)
setup_5445x_clocks();
#endif
#ifdef CONFIG_FSL_I2C
#ifdef CONFIG_SYS_FSL_I2C
gd->arch.i2c1_clk = gd->bus_clk;
#endif
......
......@@ -95,7 +95,7 @@ void cpu_init_f(void)
out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
#endif
#ifdef CONFIG_FSL_I2C
#ifdef CONFIG_SYS_I2C_FSL
out_be16(&gpio->par_feci2cirq,
GPIO_PAR_FECI2CIRQ_SCL | GPIO_PAR_FECI2CIRQ_SDA);
#endif
......
......@@ -40,7 +40,7 @@ int get_clocks(void)
gd->bus_clk = CONFIG_SYS_CLK;
gd->cpu_clk = (gd->bus_clk * 2);
#ifdef CONFIG_FSL_I2C
#ifdef CONFIG_SYS_I2C_FSL
gd->arch.i2c1_clk = gd->bus_clk;
#endif
......
......@@ -26,7 +26,7 @@
/* Architecture-specific global data */
struct arch_global_data {
#ifdef CONFIG_FSL_I2C
#ifdef CONFIG_SYS_I2C_FSL
unsigned long i2c1_clk;
unsigned long i2c2_clk;
#endif
......
......@@ -186,11 +186,11 @@ static spd_eeprom_t default_spd_eeprom = {
int vme8349_read_spd(uchar chip, uint addr, int alen, uchar *buffer, int len)
{
int old_bus = I2C_GET_BUS();
int old_bus = i2c_get_bus_num();
unsigned int l, sum;
int valid = 0;
I2C_SET_BUS(0);
i2c_set_bus_num(0);
if (i2c_read(chip, addr, alen, buffer, len) == 0)
if (memcmp(&buffer[64], &default_spd_eeprom.mid[0], 8) == 0) {
......@@ -215,7 +215,7 @@ int vme8349_read_spd(uchar chip, uint addr, int alen, uchar *buffer, int len)
buffer[63] = sum;
}
I2C_SET_BUS(old_bus);
i2c_set_bus_num(old_bus);
return 0;
}
......@@ -82,7 +82,7 @@ CONFIG_CMD_DATE -- enable to use date feature in u-boot
CONFIG_MCFTMR -- define to use DMA timer
CONFIG_MCFPIT -- define to use PIT timer
CONFIG_FSL_I2C -- define to use FSL common I2C driver
CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver
CONFIG_HARD_I2C -- define for I2C hardware support
CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
CONFIG_SYS_I2C_SPEED -- define for I2C speed
......
......@@ -90,7 +90,7 @@ MCFFEC_TOUT_LOOP -- set FEC timeout loop
CONFIG_MCFTMR -- define to use DMA timer
CONFIG_MCFPIT -- define to use PIT timer
CONFIG_FSL_I2C -- define to use FSL common I2C driver
CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver
CONFIG_HARD_I2C -- define for I2C hardware support
CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
CONFIG_SYS_I2C_SPEED -- define for I2C speed
......
......@@ -89,7 +89,7 @@ MCFFEC_TOUT_LOOP -- set FEC timeout loop
CONFIG_MCFTMR -- define to use DMA timer
CONFIG_MCFPIT -- define to use PIT timer
CONFIG_FSL_I2C -- define to use FSL common I2C driver
CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver
CONFIG_HARD_I2C -- define for I2C hardware support
CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
CONFIG_SYS_I2C_SPEED -- define for I2C speed
......
......@@ -112,7 +112,7 @@ _IO_BASE -- define for IO base address
CONFIG_MCFTMR -- define to use DMA timer
CONFIG_MCFPIT -- define to use PIT timer
CONFIG_FSL_I2C -- define to use FSL common I2C driver
CONFIG_SYS_FSL_I2C -- define to use FSL common I2C driver
CONFIG_HARD_I2C -- define for I2C hardware support
CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
CONFIG_SYS_I2C_SPEED -- define for I2C speed
......
......@@ -97,7 +97,7 @@ CONFIG_DOS_PARTITION -- enable DOS read/write
CONFIG_SLTTMR -- define to use SLT timer
CONFIG_FSL_I2C -- define to use FSL common I2C driver
CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver
CONFIG_HARD_I2C -- define for I2C hardware support
CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
CONFIG_SYS_I2C_SPEED -- define for I2C speed
......
......@@ -263,8 +263,7 @@ int misc_init_r(void)
{
int rc = 0;
#ifdef CONFIG_HARD_I2C
#if defined(CONFIG_SYS_I2C)
unsigned int orig_bus = i2c_get_bus_num();
u8 i2c_data;
......
......@@ -87,7 +87,7 @@ void pci_init_board(void)
#endif
u8 reg8;
#ifdef CONFIG_HARD_I2C
#if defined(CONFIG_SYS_I2C)
i2c_set_bus_num(1);
/* Read the PCI_M66EN jumper setting */
if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &reg8, sizeof(reg8)) == 0) ||
......
......@@ -248,7 +248,7 @@ int checkboard(void)
in_8(&cpld_data->pcba_rev) & 0x0F);
/* Initialize i2c early for rom_loc and flash bank information */
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
......
......@@ -314,29 +314,13 @@ int ivm_analyze_eeprom(unsigned char *buf, int len)
int ivm_read_eeprom(void)
{
#if defined(CONFIG_I2C_MUX)
I2C_MUX_DEVICE *dev = NULL;
#endif
uchar i2c_buffer[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
char *buf;
unsigned long dev_addr = CONFIG_SYS_IVM_EEPROM_ADR;
int ret;
#if defined(CONFIG_SYS_I2C)
buf = getenv("EEprom_ivm");
i2c_set_bus_num(buf ? (int)simple_strtol(buf, NULL, 10) : 0);
#else
#if defined(CONFIG_I2C_MUX)
/* First init the Bus, select the Bus */
buf = (unsigned char *) getenv("EEprom_ivm");
if (buf != NULL)
dev = i2c_mux_ident_muxstring(buf);
if (dev == NULL) {
printf("Error couldnt add Bus for IVM\n");
return -1;
}
i2c_set_bus_num(dev->busid);
#endif
/* add deblocking here */
i2c_make_abort();
......
......@@ -95,19 +95,6 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
{0, 0, 0, 0, QE_IOP_TAB_END},
};
static int board_init_i2c_busses(void)
{
I2C_MUX_DEVICE *dev = NULL;
uchar *dtt_bus = (uchar *)"pca9547:70:a";
/* Set up the Bus for the DTTs */
dev = i2c_mux_ident_muxstring(dtt_bus);
if (dev == NULL)
printf("Error couldn't add Bus for DTT\n");
return 0;
}
#if defined(CONFIG_SUVD3)
const uint upma_table[] = {
0x1ffedc00, 0x0ffcdc80, 0x0ffcdc80, 0x0ffcdc04, /* Words 0 to 3 */
......@@ -206,8 +193,6 @@ int board_early_init_r(void)
int misc_init_r(void)
{
/* add board specific i2c busses */
board_init_i2c_busses();
return 0;
}
......
......@@ -28,7 +28,6 @@ LIB := $(obj)libi2c.o
COBJS-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o
COBJS-$(CONFIG_DRIVER_DAVINCI_I2C) += davinci_i2c.o
COBJS-$(CONFIG_DW_I2C) += designware_i2c.o
COBJS-$(CONFIG_FSL_I2C) += fsl_i2c.o
COBJS-$(CONFIG_I2C_MVTWSI) += mvtwsi.o
COBJS-$(CONFIG_I2C_MV) += mv_i2c.o
COBJS-$(CONFIG_I2C_MXC) += mxc_i2c.o
......@@ -46,6 +45,7 @@ COBJS-$(CONFIG_U8500_I2C) += u8500_i2c.o
COBJS-$(CONFIG_SH_I2C) += sh_i2c.o
COBJS-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
COBJS-$(CONFIG_SYS_I2C) += i2c_core.o
COBJS-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
COBJS-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
COBJS-$(CONFIG_ZYNQ_I2C) += zynq_i2c.o
......
This diff is collapsed.
......@@ -459,14 +459,14 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
/* I2C */
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
#define CONFIG_HARD_I2C /* I2C with hardware support */
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_I2C_CMD_TREE
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed in Hz */
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_OFFSET 0x118000
#define CONFIG_SYS_I2C2_OFFSET 0x119000
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
/*
* RTC configuration
......
......@@ -275,12 +275,11 @@ extern unsigned long get_sdram_size(void);
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
#define CONFIG_HARD_I2C /* I2C with hardware support */
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_I2C_CMD_TREE
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/
#define CONFIG_SYS_I2C_OFFSET 0x3000
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED 400000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
/* I2C EEPROM */
#define CONFIG_CMD_EEPROM
......
......@@ -451,15 +451,14 @@ combinations. this should be removed later
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_I2C_CMD_TREE
#define CONFIG_SYS_I2C_SPEED 400800 /* I2C speed and slave address*/
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_OFFSET 0x3000
#define CONFIG_SYS_I2C2_OFFSET 0x3100
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED 400800 /* I2C speed and slave address*/
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C2_SPEED 400800 /* I2C speed and slave address*/
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
/* I2C EEPROM */
#define CONFIG_ID_EEPROM
......
......@@ -218,16 +218,16 @@
/* -------------------------------------------------------------------- */
/* Generic FreeScale hardware I2C support */
#define CONFIG_HARD_I2C
#define CONFIG_FSL_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED 400000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
#define CONFIG_CMD_I2C
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_I2C_OFFSET 0x3000
#define CONFIG_SYS_I2C2_OFFSET 0x3100
/* I2C bus configuration */
#define CONFIG_SYS_I2C_SPEED 400000
#define CONFIG_SYS_I2C_SLAVE 0x7F
/* DDR2 SO-RDIMM SPD EEPROM is at I2C0-0x51 */
#define CONFIG_SYS_SPD_BUS_NUM 0
......
......@@ -82,11 +82,11 @@
#undef CONFIG_MCFPIT
/* I2C */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C /* I2C with hw support */
#define CONFIG_SYS_I2C_SPEED 80000
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_OFFSET 0x58000
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED 80000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
......
......@@ -145,11 +145,11 @@
#undef CONFIG_MCFPIT
/* I2c */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C /* I2C with hardware support */
#define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_OFFSET 0x58000
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED 80000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
/* DSPI and Serial Flash */
......
......@@ -99,11 +99,11 @@
#undef CONFIG_MCFPIT
/* I2C */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C /* I2C with hw support */
#define CONFIG_SYS_I2C_SPEED 80000
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_OFFSET 0x00000300
#define CONFIG_SYS_I2C
#define CONFIG_SYS_i2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED 80000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi)
#define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
......
......@@ -114,11 +114,11 @@
#define CONFIG_HOSTNAME M5253DEMO
/* I2C */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C /* I2C with hw support */
#define CONFIG_SYS_I2C_SPEED 80000
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_OFFSET 0x00000280
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED 80000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C))
#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)
......
......@@ -109,11 +109,11 @@
#endif
/* I2C */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C /* I2C with hw support */
#define CONFIG_SYS_I2C_SPEED 80000
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_OFFSET 0x00000300
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED 80000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */
......
......@@ -109,11 +109,11 @@
#endif
/* I2C */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C /* I2C with hw support */
#define CONFIG_SYS_I2C_SPEED 80000
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_OFFSET 0x00000300
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED 80000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c)
#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0)
......
......@@ -101,11 +101,11 @@
#undef CONFIG_MCFPIT
/* I2C */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C /* I2C with hw support */
#define CONFIG_SYS_I2C_SPEED 80000
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_OFFSET 0x58000
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED 80000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
......
......@@ -95,11 +95,11 @@
#undef CONFIG_MCFPIT
/* I2C */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C /* I2C with hw support */
#define CONFIG_SYS_I2C_SPEED 80000
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_OFFSET 0x58000
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED 80000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
......
......@@ -95,11 +95,11 @@
#undef CONFIG_MCFPIT
/* I2C */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C /* I2C with hw support */
#define CONFIG_SYS_I2C_SPEED 80000
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_OFFSET 0x58000
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED 80000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
......
......@@ -213,7 +213,7 @@
#undef CONFIG_MCFPIT
/* I2c */
#undef CONFIG_FSL_I2C
#undef CONFIG_SYS_FSL_I2C
#undef CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
/* I2C speed and slave address */
......
......@@ -156,11 +156,11 @@
#undef CONFIG_MCFPIT
/* I2c */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C /* I2C with hardware support */
#define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_OFFSET 0x58000
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED 80000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
/* DSPI and Serial Flash */
......
......@@ -189,11 +189,11 @@
#undef CONFIG_MCFPIT
/* I2c */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C /* I2C with hardware support */
#define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_OFFSET 0x58000
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED 80000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSLI2C_OFFSET 0x58000
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
/* DSPI and Serial Flash */
......
......@@ -120,11 +120,11 @@
#endif