Commit 05512517 authored by Horatiu Vultur's avatar Horatiu Vultur Committed by Daniel Schwierzeck

MSCC: Add support for Servalt SoC family.

As Ocelot, Luton and Jaguar2, this family of SoCs are found
in Microsemi Switches solution.
Reviewed-by: Daniel Schwierzeck's avatarDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: default avatarHoratiu Vultur <horatiu.vultur@microchip.com>
parent 177c07f8
......@@ -40,6 +40,13 @@ config SOC_JR2
help
This supports MSCC Jaguar2 family of SOCs.
config SOC_SERVALT
bool "Servalt SOC Family"
select SOC_VCOREIII
select MSCC_BB_SPI
help
This supports MSCC Servalt family of SOCs.
endchoice
config SYS_CONFIG_NAME
......@@ -74,4 +81,5 @@ source "board/mscc/luton/Kconfig"
source "board/mscc/jr2/Kconfig"
source "board/mscc/servalt/Kconfig"
endmenu
......@@ -91,7 +91,7 @@ int mach_cpu_init(void)
writel(ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG);
#endif
#ifdef CONFIG_SOC_JR2
#if defined(CONFIG_SOC_JR2) || defined(CONFIG_SOC_SERVALT)
writel(ICPU_SPI_MST_CFG_FAST_READ_ENA +
ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
ICPU_SPI_MST_CFG_CLK_DIV(14), BASE_CFG + ICPU_SPI_MST_CFG);
......
......@@ -19,7 +19,8 @@ static inline int vcoreiii_train_bytelane(void)
ret = hal_vcoreiii_train_bytelane(0);
#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2)
#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
defined(CONFIG_SOC_SERVALT)
if (ret)
return ret;
ret = hal_vcoreiii_train_bytelane(1);
......
......@@ -21,6 +21,11 @@
#include <mach/jr2/jr2_devcpu_gcb.h>
#include <mach/jr2/jr2_devcpu_gcb_miim_regs.h>
#include <mach/jr2/jr2_icpu_cfg.h>
#elif defined(CONFIG_SOC_SERVALT)
#include <mach/servalt/servalt.h>
#include <mach/servalt/servalt_devcpu_gcb.h>
#include <mach/servalt/servalt_devcpu_gcb_miim_regs.h>
#include <mach/servalt/servalt_icpu_cfg.h>
#else
#error Unsupported platform
#endif
......
......@@ -161,7 +161,8 @@
#endif
#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2)
#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
defined(CONFIG_SOC_SERVALT)
#define MIPS_VCOREIII_MEMORY_16BIT 1
#endif
......@@ -239,7 +240,8 @@
ICPU_MEMCTRL_CFG_MSB_ROW_ADDR(VC3_MPAR_row_addr_cnt - 1) | \
ICPU_MEMCTRL_CFG_MSB_COL_ADDR(VC3_MPAR_col_addr_cnt - 1)
#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2)
#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
defined(CONFIG_SOC_SERVALT)
#define MSCC_MEMPARM_PERIOD \
ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF(8) | \
ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(VC3_MPAR_tREFI)
......@@ -378,7 +380,8 @@ static inline void memphy_soft_reset(void)
PAUSE();
}
#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2)
#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
defined(CONFIG_SOC_SERVALT)
static u8 training_data[] = { 0xfe, 0x11, 0x33, 0x55, 0x77, 0x99, 0xbb, 0xdd };
static inline void sleep_100ns(u32 val)
......@@ -449,7 +452,7 @@ static inline void hal_vcoreiii_ddr_failed(void)
panic("DDR init failed\n");
}
#else /* JR2 */
#else /* JR2 || ServalT */
static inline void hal_vcoreiii_ddr_reset_assert(void)
{
/* Ensure the memory controller physical iface is forced reset */
......@@ -759,7 +762,8 @@ static inline void hal_vcoreiii_init_memctl(void)
/* Wait for ZCAL to clear */
while (readl(BASE_CFG + ICPU_MEMPHY_ZCAL) & ICPU_MEMPHY_ZCAL_ZCAL_ENA)
;
#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2)
#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
defined(CONFIG_SOC_SERVALT)
/* Check no ZCAL_ERR */
if (readl(BASE_CFG + ICPU_MEMPHY_ZCAL_STAT)
& ICPU_MEMPHY_ZCAL_STAT_ZCAL_ERR)
......@@ -773,7 +777,8 @@ static inline void hal_vcoreiii_init_memctl(void)
writel(MSCC_MEMPARM_MEMCFG, BASE_CFG + ICPU_MEMCTRL_CFG);
writel(MSCC_MEMPARM_PERIOD, BASE_CFG + ICPU_MEMCTRL_REF_PERIOD);
#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2)
#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
defined(CONFIG_SOC_SERVALT)
writel(MSCC_MEMPARM_TIMING0, BASE_CFG + ICPU_MEMCTRL_TIMING0);
#else /* Luton */
clrbits_le32(BASE_CFG + ICPU_MEMCTRL_TIMING0, ((1 << 20) - 1));
......@@ -799,7 +804,7 @@ static inline void hal_vcoreiii_init_memctl(void)
hal_vcoreiii_ddr_reset_release();
writel(readl(BASE_CFG + ICPU_GPR(7)) + 1, BASE_CFG + ICPU_GPR(7));
#elif defined(CONFIG_SOC_JR2)
#elif defined(CONFIG_SOC_JR2) || defined(CONFIG_SOC_SERVALT)
writel(ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA(3),
BASE_CFG + ICPU_MEMCTRL_TERMRES_CTRL);
#else /* Luton */
......@@ -820,7 +825,8 @@ static inline void hal_vcoreiii_wait_memctl(void)
/* Settle...? */
sleep_100ns(10000);
#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2)
#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
defined(CONFIG_SOC_SERVALT)
/* Establish data contents in DDR RAM for training */
__raw_writel(0xcacafefe, ((void __iomem *)MSCC_DDR_TO));
......
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Microsemi Servalt Switch driver
*
* Copyright (c) 2018 Microsemi Corporation
*/
#ifndef _MSCC_SERVALT_H_
#define _MSCC_SERVALT_H_
#include <linux/bitops.h>
#include <dm.h>
/*
* Target offset base(s)
*/
#define MSCC_IO_ORIGIN1_OFFSET 0x70000000
#define MSCC_IO_ORIGIN1_SIZE 0x00200000
#define MSCC_IO_ORIGIN2_OFFSET 0x71000000
#define MSCC_IO_ORIGIN2_SIZE 0x01000000
#define BASE_CFG ((void __iomem *)0x70000000)
#define BASE_DEVCPU_GCB ((void __iomem *)0x71010000)
#endif
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (c) 2018 Microsemi Corporation
*/
#ifndef _MSCC_SERVALT_DEVCPU_GCB_H_
#define _MSCC_SERVALT_DEVCPU_GCB_H_
#define PERF_GPR 0x4
#define PERF_SOFT_RST 0x8
#define PERF_SOFT_RST_SOFT_NON_CFG_RST BIT(2)
#define PERF_SOFT_RST_SOFT_SWC_RST BIT(1)
#define PERF_SOFT_RST_SOFT_CHIP_RST BIT(0)
#define GPIO_GPIO_ALT(x) (0x74 + 4 * (x))
#define GPIO_GPIO_ALT1(x) (0x7c + 4 * (x))
#endif
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (c) 2018 Microsemi Corporation
*/
#ifndef _MSCC_SERVALT_DEVCPU_GCB_MIIM_REGS_H_
#define _MSCC_SERVALT_DEVCPU_GCB_MIIM_REGS_H_
#define MIIM_MII_STATUS(gi) (0xc4 + (gi * 36))
#define MIIM_MII_CMD(gi) (0xcc + (gi * 36))
#define MIIM_MII_DATA(gi) (0xd0 + (gi * 36))
#define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x) ((x) ? BIT(3) : 0)
#define MSCC_F_MII_CMD_MIIM_CMD_VLD(x) ((x) ? BIT(31) : 0)
#define MSCC_F_MII_CMD_MIIM_CMD_PHYAD(x) (GENMASK(29, 25) & ((x) << 25))
#define MSCC_F_MII_CMD_MIIM_CMD_REGAD(x) (GENMASK(24, 20) & ((x) << 20))
#define MSCC_F_MII_CMD_MIIM_CMD_WRDATA(x) (GENMASK(19, 4) & ((x) << 4))
#define MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(x) (GENMASK(2, 1) & ((x) << 1))
#define MSCC_F_MII_CMD_MIIM_CMD_SCAN(x) ((x) ? BIT(0) : 0)
#define MSCC_M_MII_DATA_MIIM_DATA_SUCCESS GENMASK(17, 16)
#define MSCC_X_MII_DATA_MIIM_DATA_RDDATA(x) (((x) >> 0) & GENMASK(15, 0))
#endif
This diff is collapsed.
......@@ -12,7 +12,7 @@
void _machine_restart(void)
{
#if defined(CONFIG_SOC_JR2)
#if defined(CONFIG_SOC_JR2) || defined(CONFIG_SOC_SERVALT)
register u32 reg = readl(BASE_CFG + ICPU_GENERAL_CTRL);
/* Set owner */
reg &= ~ICPU_GENERAL_CTRL_IF_SI_OWNER_M;
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment