Commit 064b55cf authored by Heiko Schocher's avatar Heiko Schocher Committed by Tom Rini

powerpc, 5xxx, 512x: remove support for mpc5xxx and mpc512x

There was for long time no activity in the mpx5xxx area.
We need to go further and convert to Kconfig, but it
turned out, nobody is interested anymore in mpc5xxx,
so remove it.
Signed-off-by: Heiko Schocher's avatarHeiko Schocher <hs@denx.de>
parent 88024dc5
......@@ -193,12 +193,6 @@ matrix:
- env:
- BUILDMAN="mips"
TOOLCHAIN="mips"
- env:
- BUILDMAN="mpc512x"
- env:
- BUILDMAN="mpc5xx"
- env:
- BUILDMAN="mpc5xxx"
- env:
- BUILDMAN="mpc83xx"
- env:
......
......@@ -321,12 +321,6 @@ M: Wolfgang Denk <wd@denx.de>
S: Maintained
F: arch/powerpc/
POWERPC MPC5XXX
M: Wolfgang Denk <wd@denx.de>
S: Maintained
T: git git://git.denx.de/u-boot-mpc5xxx.git
F: arch/powerpc/cpu/mpc5*/
POWERPC MPC8XX
M: Wolfgang Denk <wd@denx.de>
S: Maintained
......
......@@ -608,10 +608,6 @@ The following options need to be configured:
* Adds the "fdt" command
* The bootm command automatically updates the fdt
OF_CPU - The proper name of the cpus node (only required for
MPC512X and MPC5xxx based boards).
OF_SOC - The proper name of the soc node (only required for
MPC512X and MPC5xxx based boards).
OF_TBCLK - The timebase frequency.
OF_STDOUT_PATH - The path to the console device
......@@ -1232,7 +1228,7 @@ The following options need to be configured:
- USB Support:
At the moment only the UHCI host controller is
supported (PIP405, MIP405, MPC5200); define
supported (PIP405, MIP405); define
CONFIG_USB_UHCI to enable it.
define CONFIG_USB_KEYBOARD to enable the USB Keyboard
and define CONFIG_USB_STORAGE to enable the USB
......@@ -1240,19 +1236,6 @@ The following options need to be configured:
Note:
Supported are USB Keyboards and USB Floppy drives
(TEAC FD-05PUB).
MPC5200 USB requires additional defines:
CONFIG_USB_CLOCK
for 528 MHz Clock: 0x0001bbbb
CONFIG_PSC3_USB
for USB on PSC3
CONFIG_USB_CONFIG
for differential drivers: 0x00001000
for single ended drivers: 0x00005000
for differential drivers on PSC3: 0x00000100
for single ended drivers on PSC3: 0x00004100
CONFIG_SYS_USB_EVENT_POLL
May be defined to allow interrupt polling
instead of using asynchronous interrupts
CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the
txfilltuning field in the EHCI controller on reset.
......@@ -1894,12 +1877,6 @@ The following options need to be configured:
In such cases CONFIG_GPIO_LED_INVERTED_TABLE may be defined
with a list of GPIO LEDs that have inverted polarity.
- CAN Support: CONFIG_CAN_DRIVER
Defining CONFIG_CAN_DRIVER enables CAN driver support
on those systems that support this (optional)
feature.
- I2C Support: CONFIG_SYS_I2C
This enable the NEW i2c subsystem, and will allow you to use
......
......@@ -32,8 +32,6 @@ int platform_sys_info(struct sys_info *si)
#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
#define bi_bar bi_immr_base
#elif defined(CONFIG_MPC5xxx)
#define bi_bar bi_mbar_base
#elif defined(CONFIG_MPC83xx)
#define bi_bar bi_immrbar
#endif
......
......@@ -8,12 +8,6 @@ choice
prompt "CPU select"
optional
config MPC512X
bool "MPC512X"
config MPC5xxx
bool "MPC5xxx"
config MPC83xx
bool "MPC83xx"
select CREATE_ARCH_SYMLINK
......@@ -42,8 +36,6 @@ config 4xx
endchoice
source "arch/powerpc/cpu/mpc512x/Kconfig"
source "arch/powerpc/cpu/mpc5xxx/Kconfig"
source "arch/powerpc/cpu/mpc83xx/Kconfig"
source "arch/powerpc/cpu/mpc85xx/Kconfig"
source "arch/powerpc/cpu/mpc86xx/Kconfig"
......
menu "mpc512x CPU"
depends on MPC512X
config SYS_CPU
default "mpc512x"
choice
prompt "Target select"
optional
config TARGET_PDM360NG
bool "Support pdm360ng"
config TARGET_ARIA
bool "Support aria"
config TARGET_MECP5123
bool "Support mecp5123"
config TARGET_MPC5121ADS
bool "Support mpc5121ads"
config TARGET_AC14XX
bool "Support ac14xx"
endchoice
source "board/davedenx/aria/Kconfig"
source "board/esd/mecp5123/Kconfig"
source "board/freescale/mpc5121ads/Kconfig"
source "board/ifm/ac14xx/Kconfig"
source "board/pdm360ng/Kconfig"
endmenu
#
# (C) Copyright 2007-2009 DENX Software Engineering
#
# SPDX-License-Identifier: GPL-2.0+
#
extra-y = start.o
obj-y := cpu.o
obj-y += traps.o
obj-y += cpu_init.o
obj-y += fixed_sdram.o
obj-y += interrupts.o
obj-y += iopin.o
obj-y += serial.o
obj-y += speed.o
obj-$(CONFIG_FSL_DIU_FB) += diu.o
obj-$(CONFIG_CMD_IDE) += ide.o
obj-$(CONFIG_PCI) += pci.o
/*
* needed for arch/powerpc/cpu/mpc512x/start.S
*
* These should be auto-generated
*/
#define LPCS0AW 0x0024
#define SRAMBAR 0x00C4
#define SWCRR 0x0904
#define LPC_OFFSET 0x10000
#define CS0_CONFIG 0x00000
#define CS_CTRL 0x00020
#define CS_CTRL_ME 0x01000000 /* CS Master Enable bit */
#define EXC_OFF_SYS_RESET 0x0100
#define _START_OFFSET EXC_OFF_SYS_RESET
#
# (C) Copyright 2007-2010 DENX Software Engineering
#
# SPDX-License-Identifier: GPL-2.0+
#
PLATFORM_CPPFLAGS += -DCONFIG_E300 -msoft-float -mcpu=603e
/*
* (C) Copyright 2007-2010 DENX Software Engineering
* Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* CPU specific code for the MPC512x family.
*
* Derived from the MPC83xx code.
*/
#include <common.h>
#include <command.h>
#include <net.h>
#include <netdev.h>
#include <asm/processor.h>
#include <asm/io.h>
#if defined(CONFIG_OF_LIBFDT)
#include <fdt_support.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
int checkcpu (void)
{
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
ulong clock = gd->cpu_clk;
u32 pvr = get_pvr ();
u32 spridr = in_be32(&immr->sysconf.spridr);
char buf1[32], buf2[32];
puts ("CPU: ");
switch (spridr & 0xffff0000) {
case SPR_5121E:
puts ("MPC5121e ");
break;
default:
printf ("Unknown part ID %08x ", spridr & 0xffff0000);
}
printf ("rev. %d.%d, Core ", SVR_MJREV (spridr), SVR_MNREV (spridr));
switch (pvr & 0xffff0000) {
case PVR_E300C4:
puts ("e300c4 ");
break;
default:
puts ("unknown ");
}
printf ("at %s MHz, CSB at %s MHz (RSR=0x%04lx)\n",
strmhz(buf1, clock),
strmhz(buf2, gd->arch.csb_clk),
gd->arch.reset_status & 0xffff);
return 0;
}
int
do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
ulong msr;
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
/* Interrupts and MMU off */
__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
msr &= ~( MSR_EE | MSR_IR | MSR_DR);
__asm__ __volatile__ ("mtmsr %0"::"r" (msr));
/*
* Enable Reset Control Reg - "RSTE" is the magic word that let us go
*/
out_be32(&immap->reset.rpr, 0x52535445);
/* Verify Reset Control Reg is enabled */
while (!(in_be32(&immap->reset.rcer) & RCER_CRE))
;
printf ("Resetting the board.\n");
udelay(200);
/* Perform reset */
out_be32(&immap->reset.rcr, RCR_SWHR);
/* Unreached... */
return 1;
}
/*
* Get timebase clock frequency (like cpu_clk in Hz)
*/
unsigned long get_tbclk (void)
{
return (gd->bus_clk + 3L) / 4L;
}
#if defined(CONFIG_WATCHDOG)
void watchdog_reset (void)
{
int re_enable = disable_interrupts ();
/* Reset watchdog */
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
out_be32(&immr->wdt.swsrr, 0x556c);
out_be32(&immr->wdt.swsrr, 0xaa39);
if (re_enable)
enable_interrupts ();
}
#endif
#ifdef CONFIG_OF_LIBFDT
#ifdef CONFIG_OF_SUPPORT_OLD_DEVICE_TREES
/*
* fdt setup for old device trees
* fix up
* cpu clocks
* soc clocks
* ethernet addresses
*/
static void old_ft_cpu_setup(void *blob, bd_t *bd)
{
/*
* avoid fixing up by path because that
* produces scary error messages
*/
uchar enetaddr[6];
/*
* old device trees have ethernet nodes with
* device_type = "network"
*/
eth_getenv_enetaddr("ethaddr", enetaddr);
do_fixup_by_prop(blob, "device_type", "network", 8,
"local-mac-address", enetaddr, 6, 0);
do_fixup_by_prop(blob, "device_type", "network", 8,
"address", enetaddr, 6, 0);
/*
* old device trees have soc nodes with
* device_type = "soc"
*/
do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
"bus-frequency", bd->bi_ipsfreq, 0);
}
#endif
static void ft_clock_setup(void *blob, bd_t *bd)
{
char *cpu_path = "/cpus/" OF_CPU;
/*
* fixup cpu clocks using path
*/
do_fixup_by_path_u32(blob, cpu_path,
"timebase-frequency", OF_TBCLK, 1);
do_fixup_by_path_u32(blob, cpu_path,
"bus-frequency", bd->bi_busfreq, 1);
do_fixup_by_path_u32(blob, cpu_path,
"clock-frequency", bd->bi_intfreq, 1);
/*
* fixup soc clocks using compatible
*/
do_fixup_by_compat_u32(blob, OF_SOC_COMPAT,
"bus-frequency", bd->bi_ipsfreq, 1);
}
void ft_cpu_setup(void *blob, bd_t *bd)
{
#ifdef CONFIG_OF_SUPPORT_OLD_DEVICE_TREES
old_ft_cpu_setup(blob, bd);
#endif
ft_clock_setup(blob, bd);
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
}
#endif
#ifdef CONFIG_MPC512x_FEC
/* Default initializations for FEC controllers. To override,
* create a board-specific function called:
* int board_eth_init(bd_t *bis)
*/
int cpu_eth_init(bd_t *bis)
{
return mpc512x_fec_initialize(bis);
}
#endif
/*
* Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
* Copyright (C) 2007-2009 DENX Software Engineering
*
* SPDX-License-Identifier: GPL-2.0+
*
* Derived from the MPC83xx code.
*/
#include <common.h>
#include <asm/io.h>
#include <asm/mpc512x.h>
#include <asm/processor.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* Set up the memory map, initialize registers,
*/
void cpu_init_f (volatile immap_t * im)
{
u32 ips_div;
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
/* Clear initial global data */
memset ((void *) gd, 0, sizeof (gd_t));
/* Local Window and chip select configuration */
#if defined(CONFIG_SYS_CS0_START) && defined(CONFIG_SYS_CS0_SIZE)
out_be32(&im->sysconf.lpcs0aw,
CSAW_START(CONFIG_SYS_CS0_START) |
CSAW_STOP(CONFIG_SYS_CS0_START, CONFIG_SYS_CS0_SIZE));
sync_law(&im->sysconf.lpcs0aw);
#endif
#if defined(CONFIG_SYS_CS0_CFG)
out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
#endif
#if defined(CONFIG_SYS_CS1_START) && defined(CONFIG_SYS_CS1_SIZE)
out_be32(&im->sysconf.lpcs1aw,
CSAW_START(CONFIG_SYS_CS1_START) |
CSAW_STOP(CONFIG_SYS_CS1_START, CONFIG_SYS_CS1_SIZE));
sync_law(&im->sysconf.lpcs1aw);
#endif
#if defined(CONFIG_SYS_CS1_CFG)
out_be32(&im->lpc.cs_cfg[1], CONFIG_SYS_CS1_CFG);
#endif
#if defined(CONFIG_SYS_CS2_START) && (defined CONFIG_SYS_CS2_SIZE)
out_be32(&im->sysconf.lpcs2aw,
CSAW_START(CONFIG_SYS_CS2_START) |
CSAW_STOP(CONFIG_SYS_CS2_START, CONFIG_SYS_CS2_SIZE));
sync_law(&im->sysconf.lpcs2aw);
#endif
#if defined(CONFIG_SYS_CS2_CFG)
out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
#endif
#if defined(CONFIG_SYS_CS3_START) && defined(CONFIG_SYS_CS3_SIZE)
out_be32(&im->sysconf.lpcs3aw,
CSAW_START(CONFIG_SYS_CS3_START) |
CSAW_STOP(CONFIG_SYS_CS3_START, CONFIG_SYS_CS3_SIZE));
sync_law(&im->sysconf.lpcs3aw);
#endif
#if defined(CONFIG_SYS_CS3_CFG)
out_be32(&im->lpc.cs_cfg[3], CONFIG_SYS_CS3_CFG);
#endif
#if defined(CONFIG_SYS_CS4_START) && defined(CONFIG_SYS_CS4_SIZE)
out_be32(&im->sysconf.lpcs4aw,
CSAW_START(CONFIG_SYS_CS4_START) |
CSAW_STOP(CONFIG_SYS_CS4_START, CONFIG_SYS_CS4_SIZE));
sync_law(&im->sysconf.lpcs4aw);
#endif
#if defined(CONFIG_SYS_CS4_CFG)
out_be32(&im->lpc.cs_cfg[4], CONFIG_SYS_CS4_CFG);
#endif
#if defined(CONFIG_SYS_CS5_START) && defined(CONFIG_SYS_CS5_SIZE)
out_be32(&im->sysconf.lpcs5aw,
CSAW_START(CONFIG_SYS_CS5_START) |
CSAW_STOP(CONFIG_SYS_CS5_START, CONFIG_SYS_CS5_SIZE));
sync_law(&im->sysconf.lpcs5aw);
#endif
#if defined(CONFIG_SYS_CS5_CFG)
out_be32(&im->lpc.cs_cfg[5], CONFIG_SYS_CS5_CFG);
#endif
#if defined(CONFIG_SYS_CS6_START) && defined(CONFIG_SYS_CS6_SIZE)
out_be32(&im->sysconf.lpcs6aw,
CSAW_START(CONFIG_SYS_CS6_START) |
CSAW_STOP(CONFIG_SYS_CS6_START, CONFIG_SYS_CS6_SIZE));
sync_law(&im->sysconf.lpcs6aw);
#endif
#if defined(CONFIG_SYS_CS6_CFG)
out_be32(&im->lpc.cs_cfg[6], CONFIG_SYS_CS6_CFG);
#endif
#if defined(CONFIG_SYS_CS7_START) && defined(CONFIG_SYS_CS7_SIZE)
out_be32(&im->sysconf.lpcs7aw,
CSAW_START(CONFIG_SYS_CS7_START) |
CSAW_STOP(CONFIG_SYS_CS7_START, CONFIG_SYS_CS7_SIZE));
sync_law(&im->sysconf.lpcs7aw);
#endif
#if defined(CONFIG_SYS_CS7_CFG)
out_be32(&im->lpc.cs_cfg[7], CONFIG_SYS_CS7_CFG);
#endif
#if defined CONFIG_SYS_CS_ALETIMING
if (SVR_MJREV(in_be32(&im->sysconf.spridr)) >= 2)
out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
#endif
#if defined CONFIG_SYS_CS_BURST
out_be32(&im->lpc.cs_bcr, CONFIG_SYS_CS_BURST);
#endif
#if defined CONFIG_SYS_CS_DEADCYCLE
out_be32(&im->lpc.cs_dccr, CONFIG_SYS_CS_DEADCYCLE);
#endif
#if defined CONFIG_SYS_CS_HOLDCYCLE
out_be32(&im->lpc.cs_hccr, CONFIG_SYS_CS_HOLDCYCLE);
#endif
/* system performance tweaking */
#ifdef CONFIG_SYS_ACR_PIPE_DEP
/* Arbiter pipeline depth */
out_be32(&im->arbiter.acr,
(im->arbiter.acr & ~ACR_PIPE_DEP) |
(CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT)
);
#endif
#ifdef CONFIG_SYS_ACR_RPTCNT
/* Arbiter repeat count */
out_be32(im->arbiter.acr,
(im->arbiter.acr & ~(ACR_RPTCNT)) |
(CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT)
);
#endif
/* RSR - Reset Status Register - clear all status */
gd->arch.reset_status = im->reset.rsr;
out_be32(&im->reset.rsr, ~RSR_RES);
/*
* RMR - Reset Mode Register - enable checkstop reset
*/
out_be32(&im->reset.rmr, RMR_CSRE & (1 << RMR_CSRE_SHIFT));
/* Set IPS-CSB divider: IPS = 1/2 CSB */
ips_div = in_be32(&im->clk.scfr[0]);
ips_div &= ~(SCFR1_IPS_DIV_MASK);
ips_div |= SCFR1_IPS_DIV << SCFR1_IPS_DIV_SHIFT;
out_be32(&im->clk.scfr[0], ips_div);
#ifdef SCFR1_LPC_DIV
clrsetbits_be32(&im->clk.scfr[0], SCFR1_LPC_DIV_MASK,
SCFR1_LPC_DIV << SCFR1_LPC_DIV_SHIFT);
#endif