Commit 0e31666d authored by Chris Packham's avatar Chris Packham Committed by Stefan Roese

ARM: mvebu: add support for Allied Telesis x530

This is a range of stackable network switches. The SoC is Armada-385 and
there are a number of variants with differing network port
configurations. The DP variants are intended for a harsher operating
environment so they use a different i2c mux and fit industrial-temp
parts.
Signed-off-by: default avatarChris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese's avatarStefan Roese <sr@denx.de>
parent 0e620729
......@@ -109,7 +109,9 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
armada-xp-maxbcm.dtb \
armada-xp-synology-ds414.dtb \
armada-xp-theadorable.dtb \
armada-38x-controlcenterdc.dtb
armada-38x-controlcenterdc.dtb \
armada-385-atl-x530.dtb \
armada-385-atl-x530DP.dtb
dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \
uniphier-ld11-global.dtb \
......
// SPDX-License-Identifier: GPL-2.0
&spi1 {
u-boot,dm-pre-reloc;
spi-flash@0 {
u-boot,dm-pre-reloc;
};
};
&uart0 {
u-boot,dm-pre-reloc;
};
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "armada-385-atl-x530.dtsi"
#include "armada-385-atl-x530-u-boot.dtsi"
/ {
model = "Allied Telesis x530";
compatible = "alliedtelesis,x530", "marvell,armada385", "marvell,armada380";
nand-protect {
compatible = "atl,nand-protect";
protect-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
};
usb-enable {
compatible = "atl,usb-enable";
enable-gpio = <&gpio0 19 GPIO_ACTIVE_HIGH>;
};
boot-board {
compatible = "atl,boot-board";
present-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
override-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
};
phy-reset {
compatible = "atl,phy-reset";
reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>,
<&gpio1 21 GPIO_ACTIVE_HIGH>;
};
led-enable {
compatible = "atl,led-enable";
enable-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
};
led_7seg {
compatible = "atl,of-led-7seg";
segment-gpios = <
&led_7seg_gpio 0 0
&led_7seg_gpio 1 0
&led_7seg_gpio 2 0
&led_7seg_gpio 3 0
&led_7seg_gpio 4 0
&led_7seg_gpio 5 0
&led_7seg_gpio 6 0
&led_7seg_gpio 7 0>;
};
};
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/gpio/gpio.h>
#include "armada-385.dtsi"
/ {
model = "Allied Telesis x530";
compatible = "alliedtelesis,x530", "marvell,armada385", "marvell,armada380";
chosen {
stdout-path = "serial0:115200n8";
bootargs = "console=ttyS0,115200 earlyprintk";
};
aliases {
spi1 = &spi1;
i2c0 = &i2c0;
};
memory {
device_type = "memory";
reg = <0 0x00000000 0 0x40000000>; /* 1 GB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x3d) 0 0xf4800000 0x80000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
pcie-mem-aperture = <0xa0000000 0x40000000>;
};
eco-button-interrupt {
compatible = "atl,eco-button-interrupt";
eco-button-gpio = <&gpio0 14 GPIO_ACTIVE_LOW>;
};
board-reset {
compatible = "atl,phy_reset";
/* Physical board layout of reset pin is active-low but for the
* current driver we have to set it to active-high here.
*/
phy-reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>,
<&gpio1 21 GPIO_ACTIVE_HIGH>;
};
phy-int {
compatible = "linux,uio-pdrv-genirq";
interrupt-parent = <&gpio0>;
interrupts = <6 IRQ_TYPE_EDGE_BOTH>;
};
led-enable {
compatible = "atl,led-enable";
led-enable-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
};
led_7seg {
compatible = "atl,of-led-7seg";
segment-gpios = <
&led_7seg_gpio 0 0
&led_7seg_gpio 1 0
&led_7seg_gpio 2 0
&led_7seg_gpio 3 0
&led_7seg_gpio 4 0
&led_7seg_gpio 5 0
&led_7seg_gpio 6 0
&led_7seg_gpio 7 0>;
};
poe {
compatible = "atl,periph-poe";
poe-reset-gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>;
interrupt-parent = <&gpio0>;
interrupts = <20 IRQ_TYPE_EDGE_BOTH>;
};
};
&pciec {
status = "okay";
};
&pcie1 {
status = "okay";
};
&devbus_cs1 {
compatible = "marvell,mvebu-devbus";
status = "okay";
devbus,bus-width = <8>;
devbus,turn-off-ps = <60000>;
devbus,badr-skew-ps = <0>;
devbus,acc-first-ps = <124000>;
devbus,acc-next-ps = <248000>;
devbus,rd-setup-ps = <0>;
devbus,rd-hold-ps = <0>;
/* Write parameters */
devbus,sync-enable = <0>;
devbus,wr-high-ps = <60000>;
devbus,wr-low-ps = <60000>;
devbus,ale-wr-ps = <60000>;
nvs@0 {
status = "okay";
compatible = "mtd-ram";
reg = <0 0x00080000>;
bank-width = <1>;
label = "nvs";
};
};
&gpio0 {
poe-disable {
gpio-hog;
gpios = <16 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "poe-disable";
};
};
&gpio1 {
poe-mezz-reset {
gpio-hog;
gpios = <15 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "poe-mezz-reset";
};
};
&i2c0 {
clock-frequency = <100000>;
status = "okay";
mux@71 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nxp,pca9544";
reg = <0x71>;
i2c-mux-idle-disconnect;
i2c@0 { /* POE devices MUX */
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
rng@3b {
compatible = "maxim,ds2476";
reg = <0x3b>;
};
hwmon@2e {
compatible = "adi,adt7476";
reg = <0x2e>;
};
hwmon@2d {
compatible = "adi,adt7476";
reg = <0x2d>;
};
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
rtc@68 {
compatible = "dallas,ds1340";
reg = <0x68>;
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
led_7seg_gpio: gpio@20 {
compatible = "nxp,pca9554";
gpio-controller;
#gpio-cells = <2>;
reg = <0x20>;
};
sfpgpio: gpio@27 { /* I2C to GPIO */
compatible = "nxp,pca9555";
gpio-controller;
#gpio-cells = <2>;
reg = <0x27>;
interrupt-parent = <&gpio0>;
interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
};
sfpmux: mux@77 { /* SFP I2C MUX */
#address-cells = <1>;
#size-cells = <0>;
compatible = "nxp,pca9544";
reg = <0x77>;
i2c-mux-idle-disconnect;
};
};
};
};
&spi1 {
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <50000000>;
m25p,fast-read;
partition@u-boot {
reg = <0x00000000 0x00100000>;
label = "u-boot";
};
partition@u-boot-env {
reg = <0x00100000 0x00040000>;
label = "u-boot-env";
};
partition@unused {
reg = <0x00140000 0x00e80000>;
label = "unused";
};
partition@idprom {
reg = <0x00fc0000 0x00040000>;
label = "idprom";
};
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&usb0 {
status = "okay";
};
&refclk {
clock-frequency = <25000000>;
};
&nand_controller { /* 256 MB */
status = "okay";
num-cs = <1>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
marvell,nand-enable-arbiter;
nand-on-flash-bbt;
};
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "armada-385-atl-x530.dtsi"
#include "armada-385-atl-x530-u-boot.dtsi"
#include "armada-385-atl-x530DP.dtsi"
/ {
model = "Allied Telesis x530DP";
compatible = "alliedtelesis,x530DP", "alliedtelesis,x530", "marvell,armada385", "marvell,armada380";
nand-protect {
compatible = "atl,nand-protect";
protect-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
};
usb-enable {
compatible = "atl,usb-enable";
enable-gpio = <&gpio0 19 GPIO_ACTIVE_HIGH>;
};
boot-board {
compatible = "atl,boot-board";
present-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
override-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
};
phy-reset {
compatible = "atl,phy-reset";
reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>,
<&gpio1 21 GPIO_ACTIVE_HIGH>;
};
led-enable {
compatible = "atl,led-enable";
enable-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
};
led_7seg {
compatible = "atl,of-led-7seg";
segment-gpios = <
&led_7seg_gpio 0 0
&led_7seg_gpio 1 0
&led_7seg_gpio 2 0
&led_7seg_gpio 3 0
&led_7seg_gpio 4 0
&led_7seg_gpio 5 0
&led_7seg_gpio 6 0
&led_7seg_gpio 7 0>;
};
};
// SPDX-License-Identifier: GPL-2.0
&i2c0 {
mux@71 {
compatible = "nxp,pca9548";
i2c@1 {
hwmon@2c {
compatible = "ti,lm87";
reg = <0x2c>;
};
hwmon@2d {
compatible = "ti,lm87";
reg = <0x2d>;
};
hwmon@2e {
pwm-polarity = <1>;
};
};
psu_a_adapter: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
};
psu_b_adapter: i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
};
i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
misc_gpio: gpio@26 {
compatible = "nxp,pca9555";
gpio-controller;
#gpio-cells = <2>;
reg = <0x26>;
interrupt-parent = <&gpio0>;
interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
status = "okay";
interrupt-controller;
#interrupt-cells = <2>;
psu_bank2 {
gpio-hog;
gpios = <0 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "psu-bank2";
};
};
};
};
};
/ {
psu_slot_a {
compatible = "atl,dts-overlay-gpio-psu-slot";
slot-name = "PSU Bay A";
board-index = <1>;
present-gpio = <&misc_gpio 1 GPIO_ACTIVE_LOW>;
output-ok-gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>;
interrupt-parent = <&misc_gpio>;
interrupts = <1 IRQ_TYPE_EDGE_BOTH>;
overlay = <&psu_a_overlay>;
};
psu_slot_b {
compatible = "atl,dts-overlay-gpio-psu-slot";
slot-name = "PSU Bay B";
board-index = <2>;
present-gpio = <&misc_gpio 2 GPIO_ACTIVE_LOW>;
output-ok-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
interrupt-parent = <&misc_gpio>;
interrupts = <2 IRQ_TYPE_EDGE_BOTH>;
overlay = <&psu_b_overlay>;
};
fan_slot_a {
compatible = "atl,fan05-slot";
slot-name = "Fan Bay A";
board-index = <3>;
present-gpio = <&misc_gpio 3 GPIO_ACTIVE_LOW>;
fault-gpio = <&misc_gpio 11 GPIO_ACTIVE_LOW>;
interrupt-parent = <&misc_gpio>;
interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
overlay = <&fan_a_overlay>;
};
};
/ {
psu_a_overlay: psu_a {
fragment@0 {
target = <&psu_a_adapter>;
__overlay__ {
#address-cells = <1>;
#size-cells = <0>;
psu@51 {
compatible = "atl,atl-pwr-gen2";
reg = <0x51>;
board-index = <1>;
};
};
};
};
};
/ {
psu_b_overlay: psu_b {
fragment@0 {
target = <&psu_b_adapter>;
__overlay__ {
#address-cells = <1>;
#size-cells = <0>;
psu@51 {
compatible = "atl,atl-pwr-gen2";
reg = <0x51>;
board-index = <2>;
};
};
};
};
};
/ {
fan_a_overlay:fan_a {
fragment@1 {
target-path = "/";
__overlay__ {
fan@1 {
compatible = "atl,fan05";
board-index = <3>;
module-id-gpios =
<&misc_gpio 4 GPIO_ACTIVE_HIGH>,
<&misc_gpio 5 GPIO_ACTIVE_HIGH>,
<&misc_gpio 6 GPIO_ACTIVE_HIGH>;
};
};
};
};
};
......@@ -132,6 +132,10 @@ config TARGET_CONTROLCENTERDC
bool "Support CONTROLCENTERDC"
select 88F6820
config TARGET_X530
bool "Support Allied Telesis x530"
select 88F6820
endchoice
config SYS_BOARD
......@@ -149,6 +153,7 @@ config SYS_BOARD
default "maxbcm" if TARGET_MAXBCM
default "theadorable" if TARGET_THEADORABLE
default "a38x" if TARGET_CONTROLCENTERDC
default "x530" if TARGET_X530
config SYS_CONFIG_NAME
default "clearfog" if TARGET_CLEARFOG
......@@ -165,6 +170,7 @@ config SYS_CONFIG_NAME
default "turris_omnia" if TARGET_TURRIS_OMNIA
default "turris_mox" if TARGET_TURRIS_MOX
default "controlcenterdc" if TARGET_CONTROLCENTERDC
default "x530" if TARGET_X530
config SYS_VENDOR
default "Marvell" if TARGET_DB_MV784MP_GP
......@@ -179,6 +185,7 @@ config SYS_VENDOR
default "CZ.NIC" if TARGET_TURRIS_OMNIA
default "CZ.NIC" if TARGET_TURRIS_MOX
default "gdsys" if TARGET_CONTROLCENTERDC
default "alliedtelesis" if TARGET_X530
config SYS_SOC
default "mvebu"
......
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Allied Telesis Labs
*/
#include <common.h>
#include <dm.h>
#include <asm/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
int gpio_hog_list(struct gpio_desc *gpiod, int max_count,
const char *node_name, const char *gpio_name, int value)
{
int node;
int count;
int i;
node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, node_name);
if (node < 0)
return -ENODEV;
if (!dm_gpio_is_valid(gpiod)) {
count =
gpio_request_list_by_name_nodev(offset_to_ofnode(node),
gpio_name, gpiod, max_count,
GPIOD_IS_OUT);
if (count < 0)
return count;
for (i = 0; i < count; i++)
dm_gpio_set_value(&gpiod[i], value);
}
return 0;
}
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2017 Allied Telesis Labs
*/
int gpio_hog_list(struct gpio_desc *gpiod, int max_count, const char *node_name,
const char *gpio_name, int value);
static inline int gpio_hog(struct gpio_desc *gpiod, const char *node_name,
const char *gpio_name, int value)
{
return gpio_hog_list(gpiod, 1, node_name, gpio_name, value);
}
x530 BOARD
M: Chris Packham <chris.packham@alliedtelesis.co.nz>
S: Maintained
F: board/alliedtelesis/x530/
F: board/alliedtelesis/common/gpio_hog.c
F: board/alliedtelesis/common/gpio_hog.h
F: arch/arm/dts/armada-385-atl-x530.dts
F: arch/arm/dts/armada-385-atl-x530.dtsi
F: arch/arm/dts/armada-385-atl-x530DP.dts
F: arch/arm/dts/armada-385-atl-x530DP.dtsi
F: include/configs/x530.h
F: configs/x530_defconfig
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2017 Allied Telesis Labs
#
obj-y := $(BOARD).o
ifndef CONFIG_SPL_BUILD
obj-y += ../common/gpio_hog.o
endif
#
# Copyright (C) 2017 Allied Telesis Labs
#
# Armada XP uses version 1 image format
VERSION 1
# Boot Media configurations
BOOT_FROM spi
# Binary Header (bin_hdr) with DDR3 training code
BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017 Allied Telesis Labs
*/
#include <common.h>
#include <command.h>
#include <dm.h>
#include <i2c.h>
#include <asm/gpio.h>
#include <linux/mbus.h>
#include <linux/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include "../common/gpio_hog.h"
#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
#include <../serdes/a38x/high_speed_env_spec.h>
DECLARE_GLOBAL_DATA_PTR;
#define MVEBU_DEV_BUS_BASE (MVEBU_REGISTER(0x10400))