Commit 1895b87e authored by Horatiu Vultur's avatar Horatiu Vultur Committed by Daniel Schwierzeck

MSCC: Add support for Serval SoC family.

As Ocelot, Servalt, Luton and Jaguar2, this family of SoCs are
found in Microsemi Switches solution.
Signed-off-by: default avatarHoratiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Daniel Schwierzeck's avatarDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
parent 5c31ce36
......@@ -47,6 +47,13 @@ config SOC_SERVALT
help
This supports MSCC Servalt family of SOCs.
config SOC_SERVAL
bool "Serval SOC Family"
select SOC_VCOREIII
select MSCC_BB_SPI
help
This supports MSCC Serval family of SOCs.
endchoice
config SYS_CONFIG_NAME
......@@ -82,4 +89,6 @@ source "board/mscc/luton/Kconfig"
source "board/mscc/jr2/Kconfig"
source "board/mscc/servalt/Kconfig"
source "board/mscc/serval/Kconfig"
endmenu
......@@ -87,7 +87,7 @@ int mach_cpu_init(void)
ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG);
#else
#ifdef CONFIG_SOC_OCELOT
#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_SERVAL)
writel(ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG);
#endif
......
......@@ -20,7 +20,7 @@ static inline int vcoreiii_train_bytelane(void)
ret = hal_vcoreiii_train_bytelane(0);
#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
defined(CONFIG_SOC_SERVALT)
defined(CONFIG_SOC_SERVALT) || defined(CONFIG_SOC_SERVAL)
if (ret)
return ret;
ret = hal_vcoreiii_train_bytelane(1);
......
......@@ -26,6 +26,11 @@
#include <mach/servalt/servalt_devcpu_gcb.h>
#include <mach/servalt/servalt_devcpu_gcb_miim_regs.h>
#include <mach/servalt/servalt_icpu_cfg.h>
#elif defined(CONFIG_SOC_SERVAL)
#include <mach/serval/serval.h>
#include <mach/serval/serval_devcpu_gcb.h>
#include <mach/serval/serval_devcpu_gcb_miim_regs.h>
#include <mach/serval/serval_icpu_cfg.h>
#else
#error Unsupported platform
#endif
......
......@@ -25,7 +25,7 @@
#define VC3_MPAR_CL 6
#define VC3_MPAR_tWTR 4
#define VC3_MPAR_tRC 16
#define VC3_MPR_tFAW 16
#define VC3_MPAR_tFAW 16
#define VC3_MPAR_tRP 5
#define VC3_MPAR_tRRD 4
#define VC3_MPAR_tRCD 5
......@@ -162,7 +162,7 @@
#endif
#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
defined(CONFIG_SOC_SERVALT)
defined(CONFIG_SOC_SERVALT) || defined(CONFIG_SOC_SERVAL)
#define MIPS_VCOREIII_MEMORY_16BIT 1
#endif
......@@ -241,7 +241,7 @@
ICPU_MEMCTRL_CFG_MSB_COL_ADDR(VC3_MPAR_col_addr_cnt - 1)
#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
defined(CONFIG_SOC_SERVALT)
defined(CONFIG_SOC_SERVALT) || defined(CONFIG_SOC_SERVAL)
#define MSCC_MEMPARM_PERIOD \
ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF(8) | \
ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(VC3_MPAR_tREFI)
......@@ -381,7 +381,7 @@ static inline void memphy_soft_reset(void)
}
#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
defined(CONFIG_SOC_SERVALT)
defined(CONFIG_SOC_SERVALT) || defined(CONFIG_SOC_SERVAL)
static u8 training_data[] = { 0xfe, 0x11, 0x33, 0x55, 0x77, 0x99, 0xbb, 0xdd };
static inline void sleep_100ns(u32 val)
......@@ -452,7 +452,7 @@ static inline void hal_vcoreiii_ddr_failed(void)
panic("DDR init failed\n");
}
#else /* JR2 || ServalT */
#else /* JR2 || ServalT || Serval */
static inline void hal_vcoreiii_ddr_reset_assert(void)
{
/* Ensure the memory controller physical iface is forced reset */
......@@ -471,7 +471,7 @@ static inline void hal_vcoreiii_ddr_failed(void)
panic("DDR init failed\n");
}
#endif
#endif /* JR2 || ServalT || Serval */
/*
* DDR memory sanity checking done, possibly enable ECC.
......@@ -778,7 +778,7 @@ static inline void hal_vcoreiii_init_memctl(void)
writel(MSCC_MEMPARM_PERIOD, BASE_CFG + ICPU_MEMCTRL_REF_PERIOD);
#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
defined(CONFIG_SOC_SERVALT)
defined(CONFIG_SOC_SERVALT) || defined(CONFIG_SOC_SERVAL)
writel(MSCC_MEMPARM_TIMING0, BASE_CFG + ICPU_MEMCTRL_TIMING0);
#else /* Luton */
clrbits_le32(BASE_CFG + ICPU_MEMCTRL_TIMING0, ((1 << 20) - 1));
......@@ -793,7 +793,7 @@ static inline void hal_vcoreiii_init_memctl(void)
writel(MSCC_MEMPARM_MR2, BASE_CFG + ICPU_MEMCTRL_MR2_VAL);
writel(MSCC_MEMPARM_MR3, BASE_CFG + ICPU_MEMCTRL_MR3_VAL);
#if defined(CONFIG_SOC_OCELOT)
#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_SERVAL)
/* Termination setup - enable ODT */
writel(ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_ENA |
/* Assert ODT0 for any write */
......@@ -801,7 +801,9 @@ static inline void hal_vcoreiii_init_memctl(void)
BASE_CFG + ICPU_MEMCTRL_TERMRES_CTRL);
/* Release Reset from DDR */
#if defined(CONFIG_SOC_OCELOT)
hal_vcoreiii_ddr_reset_release();
#endif
writel(readl(BASE_CFG + ICPU_GPR(7)) + 1, BASE_CFG + ICPU_GPR(7));
#elif defined(CONFIG_SOC_JR2) || defined(CONFIG_SOC_SERVALT)
......@@ -826,7 +828,7 @@ static inline void hal_vcoreiii_wait_memctl(void)
/* Settle...? */
sleep_100ns(10000);
#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
defined(CONFIG_SOC_SERVALT)
defined(CONFIG_SOC_SERVALT) || defined(CONFIG_SOC_SERVAL)
/* Establish data contents in DDR RAM for training */
__raw_writel(0xcacafefe, ((void __iomem *)MSCC_DDR_TO));
......
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Microsemi Serval Switch driver
*
* Copyright (c) 2018 Microsemi Corporation
*/
#ifndef _MSCC_SERVAL_H_
#define _MSCC_SERVAL_H_
#include <linux/bitops.h>
#include <dm.h>
/*
* Target offset base(s)
*/
#define MSCC_IO_ORIGIN1_OFFSET 0x70000000
#define MSCC_IO_ORIGIN1_SIZE 0x00200000
#define MSCC_IO_ORIGIN2_OFFSET 0x71000000
#define MSCC_IO_ORIGIN2_SIZE 0x01000000
#define BASE_CFG ((void __iomem *)0x70000000)
#define BASE_DEVCPU_GCB ((void __iomem *)0x71070000)
#endif
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (c) 2018 Microsemi Corporation
*/
#ifndef _MSCC_SERVAL_DEVCPU_GCB_H_
#define _MSCC_SERVAL_DEVCPU_GCB_H_
#define CHIP_ID 0x0
#define PERF_GPR 0x4
#define PERF_SOFT_RST 0x8
#define PERF_SOFT_RST_SOFT_NON_CFG_RST BIT(2)
#define PERF_SOFT_RST_SOFT_SWC_RST BIT(1)
#define PERF_SOFT_RST_SOFT_CHIP_RST BIT(0)
#define GPIO_ALT(x) (0x54 + 4 * (x))
#endif
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (c) 2018 Microsemi Corporation
*/
#ifndef _MSCC_SERVAL_DEVCPU_GCB_MIIM_REGS_H_
#define _MSCC_SERVAL_DEVCPU_GCB_MIIM_REGS_H_
#define MIIM_MII_STATUS(gi) (0x5c + (gi * 36))
#define MIIM_MII_CMD(gi) (0x64 + (gi * 36))
#define MIIM_MII_DATA(gi) (0x68 + (gi * 36))
#define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x) ((x) ? BIT(3) : 0)
#define MSCC_F_MII_CMD_MIIM_CMD_VLD(x) ((x) ? BIT(31) : 0)
#define MSCC_F_MII_CMD_MIIM_CMD_PHYAD(x) (GENMASK(29, 25) & ((x) << 25))
#define MSCC_F_MII_CMD_MIIM_CMD_REGAD(x) (GENMASK(24, 20) & ((x) << 20))
#define MSCC_F_MII_CMD_MIIM_CMD_WRDATA(x) (GENMASK(19, 4) & ((x) << 4))
#define MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(x) (GENMASK(2, 1) & ((x) << 1))
#define MSCC_F_MII_CMD_MIIM_CMD_SCAN(x) ((x) ? BIT(0) : 0)
#define MSCC_M_MII_DATA_MIIM_DATA_SUCCESS GENMASK(17, 16)
#define MSCC_X_MII_DATA_MIIM_DATA_RDDATA(x) (((x) >> 0) & GENMASK(15, 0))
#endif
This diff is collapsed.
......@@ -27,7 +27,30 @@ void _machine_restart(void)
ICPU_RESET_CORE_RST_CPU_ONLY |
ICPU_RESET_CORE_RST_FORCE,
BASE_CFG + ICPU_RESET);
#else
#elif defined(CONFIG_SOC_SERVAL)
register unsigned long i;
/* Prevent VCore-III from being reset with a global reset */
writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET);
/* Do global reset */
writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST);
for (i = 0; i < 1000; i++)
;
/* Power down DDR for clean DDR re-training */
writel(readl(BASE_CFG + ICPU_MEMCTRL_CTRL) |
ICPU_MEMCTRL_CTRL_PWR_DOWN,
BASE_CFG + ICPU_MEMCTRL_CTRL);
while (!(readl(BASE_CFG + ICPU_MEMCTRL_STAT) &
ICPU_MEMCTRL_STAT_PWR_DOWN_ACK))
;
/* Reset VCore-III, only. */
writel(ICPU_RESET_CORE_RST_FORCE, BASE_CFG + ICPU_RESET);
#else /* Luton || Ocelot */
register u32 resetbits = PERF_SOFT_RST_SOFT_CHIP_RST;
(void)readl(BASE_DEVCPU_GCB + PERF_SOFT_RST);
......
......@@ -14,10 +14,11 @@
#define CONFIG_SYS_LOAD_ADDR 0x00100000
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
#define CPU_CLOCK_RATE 500000000 /* Clock for the MIPS core */
#ifdef CONFIG_SOC_LUTON
#if defined(CONFIG_SOC_LUTON) || defined(CONFIG_SOC_SERVAL)
#define CPU_CLOCK_RATE 416666666 /* Clock for the MIPS core */
#define CONFIG_SYS_MIPS_TIMER_FREQ 208333333
#else
#define CPU_CLOCK_RATE 500000000 /* Clock for the MIPS core */
#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2)
#endif
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ
......
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