Commit 1adea9cc authored by Dario Binacchi's avatar Dario Binacchi Committed by Lokesh Vutla

arm: omap: fix MPU DPLL divisor for 800MHz clock

In locked condition CLKOUT = CLKINP * [M / (N + 1)].
Signed-off-by: default avatarDario Binacchi <dariobin@libero.it>
Signed-off-by: Lokesh Vutla's avatarLokesh Vutla <lokeshvutla@ti.com>
parent ea67b26e
Pipeline #1926 failed with stages
in 0 seconds
......@@ -77,7 +77,7 @@ const struct dpll_params dpll_mpu_opp[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
{-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
{25, 0, 1, -1, -1, -1, -1}, /* OPP 100 */
{30, 0, 1, -1, -1, -1, -1}, /* OPP 120 */
{100, 3, 1, -1, -1, -1, -1}, /* OPP TB */
{100, 2, 1, -1, -1, -1, -1}, /* OPP TB */
{125, 2, 1, -1, -1, -1, -1} /* OPP NT */
},
{ /* 25 MHz */
......
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