Commit 2535d602 authored by wdenk's avatar wdenk

* Patch by Martin Krause, 17 Jul 2003:

  add delay to get I2C working with "imm" command and s3c24x0_i2c.c

* Patch by Richard Woodruff, 17 July 03:
  - Fixed bug in OMAP1510 baud rate divisor settings.

* Patch by Nye Liu, 16 July 2003:
  MPC860FADS fixes:
  - add MPC86xADS support (uses MPC86xADS.h)
  - add 866P/T core support (also MPC859T/MPC859DSL/MPC852T)
    o PLPRCR changes
    o BRG changes (EXTAL/XTAL restricted to 10MHz)
    o don't trust gclk() software measurement by default, depend on
      CONFIG_8xx_GCLK_FREQ
  - add DRAM SIMM not installed detection
  - use more "correct" SDRAM initialization sequence
  - allow different SDRAM sizes (8xxADS has 8M)
  - default DER is 0
  - remove unused MAMR defines from FADS860T.h (all done in fads.c)
  - rename MAMR/MBMR defines to be more consistent. Should eventually
    be merged into MxMR to better reflect the PowerQUICC datasheet.

* Patch by Yuli Barcohen, 16 Jul 2003:
  support new Motorola PQ2FADS-ZU evaluation board which replaced
  MPC8260ADS and MPC8266ADS
parent 945af8d7
======================================================================
Changes for U-Boot 0.4.5:
======================================================================
* Patch by Martin Krause, 17 Jul 2003:
add delay to get I2C working with "imm" command and s3c24x0_i2c.c
* Patch by Richard Woodruff, 17 July 03:
- Fixed bug in OMAP1510 baud rate divisor settings.
* Patch by Nye Liu, 16 July 2003:
MPC860FADS fixes:
- add MPC86xADS support (uses MPC86xADS.h)
- add 866P/T core support (also MPC859T/MPC859DSL/MPC852T)
o PLPRCR changes
o BRG changes (EXTAL/XTAL restricted to 10MHz)
o don't trust gclk() software measurement by default, depend on
CONFIG_8xx_GCLK_FREQ
- add DRAM SIMM not installed detection
- use more "correct" SDRAM initialization sequence
- allow different SDRAM sizes (8xxADS has 8M)
- default DER is 0
- remove unused MAMR defines from FADS860T.h (all done in fads.c)
- rename MAMR/MBMR defines to be more consistent. Should eventually
be merged into MxMR to better reflect the PowerQUICC datasheet.
* Patch by Yuli Barcohen, 16 Jul 2003:
support new Motorola PQ2FADS-ZU evaluation board which replaced
MPC8260ADS and MPC8266ADS
======================================================================
Changes for U-Boot 0.4.4:
======================================================================
......
......@@ -39,12 +39,12 @@ LIST_8xx=" \
IP860 IVML24 IVML24_128 IVML24_256 \
IVMS8 IVMS8_128 IVMS8_256 KUP4K \
LANTEC lwmon MBX MBX860T \
MHPC MVS1 NETVIA NETVIA_V2 \
NX823 pcu_e R360MPI RBC823 \
rmu RPXClassic RPXlite RRvision \
SM850 SPD823TS svm_sc8xx SXNI855T \
TOP860 TQM823L TQM823L_LCD TQM850L \
TQM855L TQM860L v37 \
MHPC MPC86xADS MVS1 NETVIA \
NETVIA_V2 NX823 pcu_e R360MPI \
RBC823 rmu RPXClassic RPXlite \
RRvision SM850 SPD823TS svm_sc8xx \
SXNI855T TOP860 TQM823L TQM823L_LCD \
TQM850L TQM855L TQM860L v37 \
"
#########################################################################
......
......@@ -227,6 +227,7 @@ ETX094_config : unconfig
FADS823_config \
FADS850SAR_config \
MPC86xADS_config \
FADS860T_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8xx fads
......
......@@ -197,7 +197,7 @@ Directory Hierarchy:
- board/lwmon Files specific to LWMON boards
- board/mbx8xx Files specific to MBX boards
- board/mpc8260ads
Files specific to MMPC8260ADS boards
Files specific to MPC8260ADS and PQ2FADS-ZU boards
- board/mpl/ Files specific to boards manufactured by MPL
- board/mpl/common Common files for MPL boards
- board/mpl/pip405 Files specific to PIP405 boards
......@@ -383,6 +383,14 @@ The following options need to be configured:
the lcd display every second with
a "rotator" |\-/|\-/
- Board flavour: (if CONFIG_MPC8260ADS is defined)
CONFIG_ADSTYPE
Possible values are:
CFG_8260ADS - original MPC8260ADS
CFG_8266ADS - MPC8266ADS (untested)
CFG_PQ2FADS - PQ2FADS-ZU
- MPC824X Family Member (if CONFIG_MPC824X is defined)
Define exactly one of
CONFIG_MPC8240, CONFIG_MPC8245
......@@ -989,8 +997,8 @@ The following options need to be configured:
is FALSE, it clears it (low).
eg: #define I2C_SDA(bit) \
if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
else immr->im_cpm.cp_pbdat &= ~PB_SDA
if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
else immr->im_cpm.cp_pbdat &= ~PB_SDA
I2C_SCL(bit)
......@@ -998,8 +1006,8 @@ The following options need to be configured:
is FALSE, it clears it (low).
eg: #define I2C_SCL(bit) \
if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
else immr->im_cpm.cp_pbdat &= ~PB_SCL
if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
else immr->im_cpm.cp_pbdat &= ~PB_SCL
I2C_DELAY
......@@ -1687,9 +1695,10 @@ Low Level (hardware related) configuration options:
- CFG_DEFAULT_IMMR:
Default address of the IMMR after system reset.
Needed on some 8260 systems (MPC8260ADS and RPXsuper)
to be able to adjust the position of the IMMR
register after a reset.
Needed on some 8260 systems (MPC8260ADS, PQ2FADS-ZU,
and RPXsuper) to be able to adjust the position of
the IMMR register after a reset.
- Floppy Disk Support:
CFG_FDC_DRIVE_NUMBER
......@@ -1862,7 +1871,7 @@ configurations; the following names are supported:
GENIETV_config TQM823L_config PIP405_config
GEN860T_config EBONY_config FPS860L_config
ELPT860_config cmi_mpc5xx_config NETVIA_config
at91rm9200dk_config omap1510inn_config
at91rm9200dk_config omap1510inn_config MPC8260ADS_config
Note: for some board special configuration names may exist; check if
additional information is available from the board vendor; for
......
......@@ -254,7 +254,7 @@ long int initdram (int board_type)
upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
memctl->memc_mbmr = MAMR_GPL_B4DIS;
memctl->memc_mbmr = MBMR_GPL_B4DIS; /* should this be mamr? - NTL */
memctl->memc_mptpr = MPTPR_PTP_DIV64;
memctl->memc_mar = 0x00008800;
......
This diff is collapsed.
......@@ -128,7 +128,7 @@ long int initdram (int board_type)
/* That should do it, just enable the periodic refresh in burst of 4*/
memctl->memc_mamr = CFG_MAMR_48_SDR | MAMR_TLFA_4X;
memctl->memc_mamr |= (MAMR_PTAE | MAMR_GPL_B4DIS);
memctl->memc_mamr |= (MAMR_PTAE | MAMR_GPL_A4DIS);
size_b0 = 16*1024*1024;
......@@ -141,7 +141,7 @@ long int initdram (int board_type)
upmconfig(UPMB, (uint *)dsp_disp_table, sizeof(dsp_disp_table)/sizeof(uint));
memctl->memc_mbmr = MAMR_GPL_B4DIS;
memctl->memc_mbmr = MBMR_GPL_B4DIS;
memctl->memc_or4 = CFG_OR4;
memctl->memc_br4 = CFG_BR4;
......
......@@ -163,7 +163,7 @@ long int initdram (int board_type)
memctl->memc_mcr = 0x80804105; /* SDRAM bank 1 */
/* Execute refresh 8 times */
memctl->memc_mbmr = (CFG_MBMR_8COL & ~MAMR_TLFB_MSK) | MAMR_TLFB_8X ;
memctl->memc_mbmr = (CFG_MBMR_8COL & ~MBMR_TLFB_MSK) | MBMR_TLFB_8X ;
memctl->memc_mcr = 0x80802130; /* SDRAM bank 0 - execute twice */
......
......@@ -218,7 +218,7 @@ int _initsdram (uint base, uint * noMbytes)
sizeof (fpga_table) / sizeof (uint));
/* Enable UPWAITB */
mc->memc_mbmr = MAMR_GPL_B4DIS; /* (16-13) */
mc->memc_mbmr = MBMR_GPL_B4DIS; /* (16-13) */
/* CS2, base FPGA_2_BASE - 4 MByte, use UPM B 32 Bit */
mc->memc_or2 = 0xffc00000 | OR_BI;
......
......@@ -246,14 +246,14 @@ initdram (int board_type)
udelay(1);
memctl->memc_mcr = 0x80806130; /* autorefresh */
memctl->memc_mbmr |= MAMR_PTBE; /* refresh enabled */
memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */
/*
* Check Bank 0 Memory Size for re-configuration
*/
size_b0 = dram_size (CFG_MBMR_8COL, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
memctl->memc_mbmr = CFG_MBMR_8COL | MAMR_PTBE;
memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE;
return (size_b0);
}
......
......@@ -149,7 +149,7 @@ long int initdram (int board_type)
udelay(1); /* 0x80006106 */
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x06);
memctl->memc_mamr |= MAMR_PTBE; /* refresh enabled */
memctl->memc_mamr |= MAMR_PTAE; /* refresh enabled */
udelay(200);
......@@ -170,7 +170,7 @@ long int initdram (int board_type)
(ulong *)SDRAM_BASE3_PRELIM,
SDRAM_MAX_SIZE);
memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTBE;
memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTAE;
/*
* Final mapping:
......
......@@ -246,7 +246,7 @@ long int initdram (int board_type)
udelay (1); /* 0x80006106 */
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x06);
memctl->memc_mamr |= MAMR_PTBE; /* refresh enabled */
memctl->memc_mamr |= MAMR_PTAE; /* refresh enabled */
udelay (200);
......@@ -276,11 +276,11 @@ long int initdram (int board_type)
if (size8 < size9) { /* leave configuration at 9 columns */
size_b0 = size9;
memctl->memc_mamr = CFG_MAMR_9COL | MAMR_PTBE;
memctl->memc_mamr = CFG_MAMR_9COL | MAMR_PTAE;
udelay (500);
} else { /* back to 8 columns */
size_b0 = size8;
memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTBE;
memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTAE;
udelay (500);
}
......
......@@ -198,11 +198,19 @@ void reset_phy (void)
vu_long *bcsr = (vu_long *)CFG_BCSR;
/* reset the FEC port */
bcsr[1] &= ~FETH_RST;
bcsr[1] &= ~FETH1_RST;
udelay(2);
bcsr[1] |= FETH_RST;
bcsr[1] |= FETH1_RST;
udelay(1000);
#ifdef CONFIG_MII
#if CONFIG_ADSTYPE == CFG_PQ2FADS
/*
* Do not bypass Rx/Tx (de)scrambler (fix configuration error)
* Enable autonegotiation.
*/
miiphy_write(0, 16, 0x610);
miiphy_write(0, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
#else
/*
* Ethernet PHY is configured (by means of configuration pins)
* to work at 10Mb/s only. We reconfigure it using MII
......@@ -212,6 +220,7 @@ void reset_phy (void)
miiphy_write(0, PHY_ANAR, 0x01E1); /* Advertise all capabilities */
miiphy_write(0, PHY_DCR, 0x0000); /* Do not bypass Rx/Tx (de)scrambler */
miiphy_write(0, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
#endif /* CONFIG_MII */
}
......@@ -219,7 +228,7 @@ int board_pre_init (void)
{
vu_long *bcsr = (vu_long *)CFG_BCSR;
bcsr[1] = ~FETHIEN & ~RS232EN_1;
bcsr[1] = ~FETHIEN1 & ~RS232EN_1;
return 0;
}
......@@ -231,12 +240,10 @@ long int initdram (int board_type)
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
volatile uchar *ramaddr, c = 0xff;
/* Initialisation is for 16MB DIMM the board is shipped with */
long int msize = 16;
uint or = 0xFF000CA0;
uint psdmr = CFG_PSDMR;
uint psrt = CFG_PSRT;
long int msize;
uint or;
uint psdmr;
uint psrt;
int i;
......@@ -246,22 +253,29 @@ long int initdram (int board_type)
immap->im_siu_conf.sc_tescr1 = 0x00004000;
memctl->memc_mptpr = CFG_MPTPR;
/* init local sdram, bank 4 */
memctl->memc_lsrt = 0x00000010;
#ifdef CFG_LSDRAM_BASE
/* Init local bus SDRAM */
memctl->memc_lsrt = CFG_LSRT;
#if CONFIG_ADSTYPE == CFG_PQ2FADS /* CS3 */
memctl->memc_or3 = 0xFF803280;
memctl->memc_br3 = CFG_LSDRAM_BASE | 0x00001861;
#else /* CS4 */
memctl->memc_or4 = 0xFFC01480;
memctl->memc_br4 = 0x04001861;
memctl->memc_lsdmr = 0x2886A522;
memctl->memc_br4 = CFG_LSDRAM_BASE | 0x00001861;
#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
memctl->memc_lsdmr = CFG_LSDMR | 0x28000000;
ramaddr = (uchar *) CFG_LSDRAM_BASE;
*ramaddr = c;
memctl->memc_lsdmr = 0x0886A522;
memctl->memc_lsdmr = CFG_LSDMR | 0x08000000;
for (i = 0; i < 8; i++) {
*ramaddr = c;
}
memctl->memc_lsdmr = 0x1886A522;
memctl->memc_lsdmr = CFG_LSDMR | 0x18000000;
*ramaddr = c;
memctl->memc_lsdmr = 0x4086A522;
memctl->memc_lsdmr = CFG_LSDMR | 0x40000000;
#endif /* CFG_LSDRAM_BASE */
/* init sdram dimm */
/* Init 60x bus SDRAM */
#ifdef CONFIG_SPD_EEPROM
{
spd_eeprom_t spd;
......@@ -398,6 +412,16 @@ long int initdram (int board_type)
printf ("OR=%X, PSDMR=%08X, PSRT=%0X\n", or, psdmr, psrt);
#endif /* SPD_DEBUG */
}
#else /* !CONFIG_SPD_EEPROM */
#if CONFIG_ADSTYPE == CFG_PQ2FADS
msize = 32;
or = 0xFE002EC0;
#else
msize = 16;
or = 0xFF000CA0;
#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
psdmr = CFG_PSDMR;
psrt = CFG_PSRT;
#endif /* CONFIG_SPD_EEPROM */
memctl->memc_psrt = psrt;
memctl->memc_or2 = or;
......@@ -415,12 +439,20 @@ long int initdram (int board_type)
*ramaddr = c;
#endif
/* return total ram size of DIMM */
/* return total 60x bus SDRAM size */
return (msize * 1024 * 1024);
}
int checkboard (void)
{
#if CONFIG_ADSTYPE == CFG_8260ADS
puts ("Board: Motorola MPC8260ADS\n");
#elif CONFIG_ADSTYPE == CFG_8266ADS
puts ("Board: Motorola MPC8266ADS\n");
#elif CONFIG_ADSTYPE == CFG_PQ2FADS
puts ("Board: Motorola PQ2FADS-ZU\n");
#else
puts ("Board: unknown\n");
#endif
return 0;
}
......@@ -57,7 +57,6 @@ SECTIONS
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mpc8xx/start.o (.text)
cpu/mpc8xx/speed.o (.text)
common/dlmalloc.o (.text)
lib_ppc/ppcstring.o (.text)
lib_generic/vsprintf.o (.text)
......@@ -67,7 +66,6 @@ SECTIONS
lib_generic/string.o (.text)
lib_ppc/extable.o (.text)
lib_ppc/kgdb.o (.text)
/* lib_ppc/ticks.o (.text) */
. = env_offset;
common/environment.o(.text)
......
......@@ -205,7 +205,7 @@ long int initdram (int board_type)
memctl->memc_br3 = CFG_BR3_CAN;
/* Initialize MBMR */
memctl->memc_mbmr = MAMR_GPL_B4DIS; /* GPL_B4 works as UPWAITB */
memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 works as UPWAITB */
/* Initialize UPMB for CAN: single read */
memctl->memc_mdr = 0xFFFFC004;
......
......@@ -267,7 +267,7 @@ void can_driver_enable (void)
volatile memctl8xx_t *memctl = &immap->im_memctl;
/* Initialize MBMR */
memctl->memc_mbmr = MAMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */
memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */
/* Initialize UPMB for CAN: single read */
memctl->memc_mdr = 0xFFFFC004;
......
......@@ -217,9 +217,9 @@ initdram (int board_type)
#endif /* XXX */
reg = memctl->memc_mamr;
reg &= ~MAMR_TLFB_MSK; /* switch timer loop ... */
reg |= MAMR_TLFB_4X; /* ... to 4x */
reg |= MAMR_PTBE; /* enable refresh */
reg &= ~MAMR_TLFA_MSK; /* switch timer loop ... */
reg |= MAMR_TLFA_4X; /* ... to 4x */
reg |= MAMR_PTAE; /* enable refresh */
memctl->memc_mamr = reg;
udelay(200);
......@@ -246,7 +246,7 @@ initdram (int board_type)
size_b0 = dram_size (CFG_MAMR, (ulong *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
#endif /* XXX */
memctl->memc_mamr = CFG_MAMR | MAMR_PTBE;
memctl->memc_mamr = CFG_MAMR | MAMR_PTAE;
/*
* Final mapping:
......
......@@ -200,14 +200,14 @@ initdram (int board_type)
udelay(1);
memctl->memc_mcr = 0x80806106;
memctl->memc_mbmr |= MAMR_PTBE; /* refresh enabled */
memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */
/*
* Check Bank 0 Memory Size for re-configuration
*/
size_b0 = dram_size (CFG_MBMR_8COL, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
memctl->memc_mbmr = CFG_MBMR_8COL | MAMR_PTBE;
memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE;
return (size_b0);
}
......
......@@ -140,7 +140,7 @@ long int initdram (int board_type)
memctl->memc_br3 = CFG_BR3_CAN;
/* Initialize MBMR */
memctl->memc_mamr = MAMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */
memctl->memc_mamr = MAMR_GPL_A4DIS; /* GPL_A4 ouput line Disable */
/* Initialize UPMB for CAN: single read */
memctl->memc_mdr = 0xFFFFC004;
......
......@@ -507,6 +507,9 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[])
if(i2c_write(chip, addr, alen, (char *)&data, size) != 0) {
printf("Error writing the chip.\n");
}
#ifdef CFG_EEPROM_PAGE_WRITE_DELAY_MS
udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
#endif
if (incrflag)
addr += size;
}
......
......@@ -42,12 +42,23 @@
static char *cpu_warning = "\n " \
"*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***";
#if ((defined(CONFIG_MPC860) || defined(CONFIG_MPC855)) && \
#if ((defined(CONFIG_MPC86x) || defined(CONFIG_MPC855)) && \
!defined(CONFIG_MPC862))
# ifdef CONFIG_MPC855
# if defined(CONFIG_MPC855)
# define ID_STR "PC855"
# elif defined(CONFIG_MPC852T)
# define ID_STR "PC852T"
# elif defined(CONFIG_MPC859T)
# define ID_STR "PC859T"
# elif defined(CONFIG_MPC859DSL)
# define ID_STR "PC859DSL"
# elif defined(CONFIG_MPC860P)
# define ID_STR "PC860P"
# elif defined(CONFIG_MPC866T)
# define ID_STR "PC866T"
# else
# define ID_STR "PC860"
# define ID_STR "PC86x" /* unknown 86x chip */
# endif
static int check_CPU (long clock, uint pvr, uint immr)
......@@ -68,6 +79,10 @@ static int check_CPU (long clock, uint pvr, uint immr)
m = 0;
switch (k) {
#ifdef CONFIG_MPC866_et_al
/* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */
case 0x08000003: pre = 'M'; suf = ""; m = 1; break;
#else
case 0x00020001: pre = 'p'; suf = ""; break;
case 0x00030001: suf = ""; break;
case 0x00120003: suf = "A"; break;
......@@ -76,17 +91,16 @@ static int check_CPU (long clock, uint pvr, uint immr)
case 0x00200004: suf = "B"; break;
case 0x00300004: suf = "C"; break;
case 0x00310004: suf = "C1"; m = 1;
break;
case 0x00310004: suf = "C1"; m = 1; break;
case 0x00200064: mid = "SR"; suf = "B"; break;
case 0x00300065: mid = "SR"; suf = "C"; break;
case 0x00310065: mid = "SR"; suf = "C1"; m = 1; break;
case 0x05010000: suf = "D3"; m = 1; break;
case 0x05020000: suf = "D4"; m = 1; break;
/* this value is not documented anywhere */
case 0x40000000: pre = 'P'; suf = "D"; m = 1; break;
#endif
default: suf = NULL; break;
}
......@@ -101,7 +115,7 @@ static int check_CPU (long clock, uint pvr, uint immr)
printf (" %u kB I-Cache", checkicache () >> 10);
printf (" %u kB D-Cache", checkdcache () >> 10);
/* lets check and see if we're running on a 860T (or P?) */
/* do we have a FEC (860T/P or 852/859/866)? */
immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
......@@ -114,6 +128,12 @@ static int check_CPU (long clock, uint pvr, uint immr)
putc ('\n');
#ifdef DEBUG
if(clock != measure_gclk()) {
printf ("clock %ldHz != %dHz\n", clock, measure_gclk());
}
#endif
return 0;
}
......@@ -316,7 +336,7 @@ int checkicache (void)
volatile memctl8xx_t *memctl = &immap->im_memctl;
u32 cacheon = rd_ic_cst () & IDC_ENABLED;
#ifdef CONFIG_IP860
#ifdef CONFIG_IP86x
u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */
#else
u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
......@@ -363,7 +383,7 @@ int checkdcache (void)
volatile memctl8xx_t *memctl = &immap->im_memctl;
u32 cacheon = rd_dc_cst () & IDC_ENABLED;
#ifdef CONFIG_IP860
#ifdef CONFIG_IP86x
u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */
#else
u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
......@@ -462,8 +482,20 @@ unsigned long get_tbclk (void)
if (immr->im_clkrst.car_sccr & SCCR_TBS) {
return (gd->cpu_clk / 16);
}
factor = (((CFG_PLPRCR) & PLPRCR_MF_MSK) >> PLPRCR_MF_SHIFT) + 1;
#define PLPRCR_val(a) (((CFG_PLPRCR) & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
#ifdef CONFIG_MPC866_et_al
/* MFN
MFI + -------
MFD + 1
factor = -----------------
(PDF + 1) * 2^S
*/
factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN)/(PLPRCR_val(MFD)+1))/
(PLPRCR_val(PDF)+1) / (1<<PLPRCR_val(S));
#else
factor = PLPRCR_val(MF)+1;
#endif
oscclk = gd->cpu_clk / factor;
......
......@@ -145,6 +145,7 @@ void cpu_init_f (volatile immap_t * immr)
defined(CONFIG_RPXCLASSIC) || \
defined(CONFIG_RPXLITE) || \
defined(CONFIG_SPD823TS) || \
defined(CONFIG_MPC86xADS) || \
(defined(CONFIG_MPC860T) && defined(CONFIG_FADS))
memctl->memc_br0 = CFG_BR0_PRELIM;
......
......@@ -217,7 +217,8 @@ static int fec_init(struct eth_device* dev, bd_t * bd)
volatile immap_t *immr = (immap_t *) CFG_IMMR;
volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
#if defined(CONFIG_FADS) && defined(CONFIG_MPC860T)
#if defined(CONFIG_FADS) && \
( defined(CONFIG_MPC860T) || defined(CONFIG_MPC866_et_al) )
/* configure FADS for fast (FEC) ethernet, half-duplex */
/* The LXT970 needs about 50ms to recover from reset, so
* wait for it by discovering the PHY before leaving eth_init().
......
......@@ -334,7 +334,11 @@ void timer_interrupt (struct pt_regs *regs)
/* Reset Timer Expired and Timers Interrupt Status */
immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
__asm__ ("nop");
#ifdef CONFIG_MPC866_et_al
immr->im_clkrst.car_plprcr |= PLPRCR_TEXPS;
#else
immr->im_clkrst.car_plprcr |= PLPRCR_TEXPS | PLPRCR_TMIST;
#endif
/* Restore Decrementer Count */
set_dec (decrementer_count);
......
......@@ -192,9 +192,9 @@ static int scc_init(struct eth_device* dev, bd_t *bis)
volatile immap_t *immr = (immap_t *)CFG_IMMR;
#if defined(CONFIG_FADS)
#if defined(CONFIG_MPC860T)
/* The FADS860T doesn't use the MODEM_EN or DATA_VOICE signals. */
#ifdef CONFIG_FADS
#if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC860T)
/* The MPC86xADS/FADS860T don't use the MODEM_EN or DATA_VOICE signals. */
*((uint *) BCSR4) &= ~BCSR4_ETHLOOP;
*((uint *) BCSR4) |= BCSR4_TFPLDL|BCSR4_TPSQEL;
*((uint *) BCSR1) &= ~BCSR1_ETHEN;
......
......@@ -68,6 +68,23 @@
#error "console not correctly defined"
#endif
static void serial_setdivisor(volatile cpm8xx_t *cp)
{
DECLARE_GLOBAL_DATA_PTR;
int divisor=gd->cpu_clk/16/gd->baudrate;
if(divisor/16>0x1000) {
/* bad divisor, assume 50Mhz clock and 9600 baud */
divisor=(50*1000*1000)/16/9600;
}
if(divisor<=0x1000) {
cp->cp_brgc1=((divisor-1)<<1) | CPM_BRG_EN;
} else {
cp->cp_brgc1=((divisor/16-1)<<1) | CPM_BRG_EN | CPM_BRG_DIV16;
}
}
#if (defined (CONFIG_8xx_CONS_SMC1) || defined (CONFIG_8xx_CONS_SMC2))