Commit 2f8d0677 authored by Gregory CLEMENT's avatar Gregory CLEMENT Committed by Daniel Schwierzeck

MIPS: mscc: ocelot: add switch reset support

On some ocelots platform a workaround is needed in order to be able to
reset the switch without resetting the DDR.
Signed-off-by: default avatarGregory CLEMENT <gregory.clement@bootlin.com>
parent c8546163
......@@ -10,6 +10,7 @@
#include <environment.h>
#include <spi.h>
#include <led.h>
#include <wait_bit.h>
DECLARE_GLOBAL_DATA_PTR;
......@@ -18,6 +19,29 @@ enum {
BOARD_TYPE_PCB123,
};
void mscc_switch_reset(bool enter)
{
/* Nasty workaround to avoid GPIO19 (DDR!) being reset */
mscc_gpio_set_alternate(19, 2);
debug("applying SwC reset\n");
writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET);
writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST);
if (wait_for_bit_le32(BASE_DEVCPU_GCB + PERF_SOFT_RST,
PERF_SOFT_RST_SOFT_CHIP_RST, false, 5000, false))
pr_err("Tiemout while waiting for switch reset\n");
/*
* Reset GPIO19 mode back as regular GPIO, output, high (DDR
* not reset) (Order is important)
*/
setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET);
mscc_gpio_set_alternate(19, 0);
}
void board_debug_uart_init(void)
{
/* too early for the pinctrl driver, so configure the UART pins here */
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment