Commit 3fafced7 authored by Rick Chen's avatar Rick Chen Committed by Tom Rini

riscv: doc: Add relative doc to describe RISC-V

Add documents to describe NX25 and AE250.
Also update other documents for RISC-V.
Signed-off-by: Rick Chen's avatarRick Chen <rick@andestech.com>
Signed-off-by: default avatarRick Chen <rickchen36@gmail.com>
Signed-off-by: default avatarGreentime Hu <green.hu@gmail.com>
parent 068feb9b
......@@ -143,6 +143,7 @@ Directory Hierarchy:
/nios2 Files generic to Altera NIOS2 architecture
/openrisc Files generic to OpenRISC architecture
/powerpc Files generic to PowerPC architecture
/riscv Files generic to RISC-V architecture
/sandbox Files generic to HW-independent "sandbox"
/sh Files generic to SH architecture
/x86 Files generic to x86 architecture
......@@ -3510,7 +3511,7 @@ Low Level (hardware related) configuration options:
globally (CONFIG_CMD_MEMORY).
- CONFIG_SKIP_LOWLEVEL_INIT
[ARM, NDS32, MIPS only] If this variable is defined, then certain
[ARM, NDS32, MIPS, RISC-V only] If this variable is defined, then certain
low level initializations (like setting up the memory
controller) are omitted and/or U-Boot does not
relocate itself into RAM.
......@@ -4964,6 +4965,22 @@ On NDS32, the following registers are used:
NOTE: DECLARE_GLOBAL_DATA_PTR must be used with file-global scope,
or current versions of GCC may "optimize" the code too much.
On RISC-V, the following registers are used:
x0: hard-wired zero (zero)
x1: return address (ra)
x2: stack pointer (sp)
x3: global pointer (gp)
x4: thread pointer (tp)
x5: link register (t0)
x8: frame pointer (fp)
x10-x11: arguments/return values (a0-1)
x12-x17: arguments (a2-7)
x28-31: temporaries (t3-6)
pc: program counter (pc)
==> U-Boot will use gp to hold a pointer to the global data
Memory Management:
------------------
......
NX25 is Andes CPU IP to adopt RISC-V architecture.
Features
========
CPU Core
- 5-stage in-order execution pipeline
- Hardware Multiplier
- radix-2/radix-4/radix-16/radix-256/fast
- Hardware Divider
- Optional branch prediction
- Machine mode and optional user mode
- Optional performance monitoring
ISA
- RV64I base integer instructions
- RVC for 16-bit compressed instructions
- RVM for multiplication and division instructions
Memory subsystem
- I & D local memory
- Size: 4KB to 16MB
- Memory subsyetem soft-error protection
- Protection scheme: parity-checking or error-checking-and-correction (ECC)
- Automatic hardware error correction
Bus
- Interface Protocol
- Synchronous AHB (32-bit/64-bit data-width), or
- Synchronous AXI4 (64-bit data-width)
Power management
- Wait for interrupt (WFI) mode
Debug
- Configurable number of breakpoints: 2/4/8
- External Debug Module
- AHB slave port
- External JTAG debug transport module
Platform Level Interrupt Controller (PLIC)
- AHB slave port
- Configurable number of interrupts: 1-1023
- Configurable number of interrupt priorities: 3/7/15/63/127/255
- Configurable number of targets: 1-16
- Preempted interrupt priority stack
Andes Technology SoC AE250
===========================
AE250 is the mainline SoC produced by Andes Technology using NX25 CPU core
base on RISC-V architecture.
AE250 has integrated both AHB and APB bus and many periphals for application
and product development.
NX25-AE250
=========
NX25-AE250 is the SoC with AE250 hardcore CPU.
Configurations
==============
CONFIG_SKIP_LOWLEVEL_INIT:
If you want to boot this system from SPI ROM and bypass e-bios (the
other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT
in "include/configs/nx25-ae250.h".
Build and boot steps
====================
build:
1. Prepare the toolchains and make sure the $PATH to toolchains is correct.
2. Use `make nx25-ae250_defconfig` in u-boot root to build the image.
Verification
====================
Target
====================
1. startup
2. relocation
3. timer driver
4. uart driver
5. mac driver
6. mmc driver
7. spi driver
Steps
====================
1. Define CONFIG_SKIP_LOWLEVEL_INIT to build u-boot which is loaded via gdb from ram.
2. Undefine CONFIG_SKIP_LOWLEVEL_INIT to build u-boot which is booted from spi rom.
3. Ping a server by mac driver
4. Scan sd card and copy u-boot image which is booted from flash to ram by sd driver.
5. Burn this u-boot image to spi rom by spi driver
6. Re-boot u-boot from spi flash with power off and power on.
Messages
====================
U-Boot 2018.01-rc2-00033-g824f89a (Dec 21 2017 - 16:51:26 +0800)
DRAM: 1 GiB
MMC: mmc@f0e00000: 0
SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB
In: serial@f0300000
Out: serial@f0300000
Err: serial@f0300000
Net:
Warning: mac@e0100000 (eth0) using random MAC address - be:dd:d7:e4:e8:10
eth0: mac@e0100000
RISC-V # version
U-Boot 2018.01-rc2-00033-gb265b91-dirty (Dec 22 2017 - 13:54:21 +0800)
riscv32-unknown-linux-gnu-gcc (GCC) 7.2.0
GNU ld (GNU Binutils) 2.29
RISC-V # setenv ipaddr 10.0.4.200 ;
RISC-V # setenv serverip 10.0.4.97 ;
RISC-V # ping 10.0.4.97 ;
Using mac@e0100000 device
host 10.0.4.97 is alive
RISC-V # mmc rescan
RISC-V # fatls mmc 0:1
318907 u-boot-ae250-64.bin
1252 hello_world_ae250_32.bin
328787 u-boot-ae250-32.bin
3 file(s), 0 dir(s)
RISC-V # sf probe 0:0 50000000 0
SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB
RISC-V # sf test 0x100000 0x1000
SPI flash test:
0 erase: 36 ticks, 111 KiB/s 0.888 Mbps
1 check: 29 ticks, 137 KiB/s 1.096 Mbps
2 write: 40 ticks, 100 KiB/s 0.800 Mbps
3 read: 20 ticks, 200 KiB/s 1.600 Mbps
Test passed
0 erase: 36 ticks, 111 KiB/s 0.888 Mbps
1 check: 29 ticks, 137 KiB/s 1.096 Mbps
2 write: 40 ticks, 100 KiB/s 0.800 Mbps
3 read: 20 ticks, 200 KiB/s 1.600 Mbps
RISC-V # fatload mmc 0:1 0x600000 u-boot-ae250-32.bin
reading u-boot-ae250-32.bin
328787 bytes read in 324 ms (990.2 KiB/s)
RISC-V # sf erase 0x0 0x51000
SF: 331776 bytes @ 0x0 Erased: OK
RISC-V # sf write 0x600000 0x0 0x50453
device 0 offset 0x0, size 0x50453
SF: 328787 bytes @ 0x0 Written: OK
RISC-V # crc32 0x600000 0x50453
crc32 for 00600000 ... 00650452 ==> 692dc44a
RISC-V # crc32 0x80000000 0x50453
crc32 for 80000000 ... 80050452 ==> 692dc44a
RISC-V #
*** power-off and power-on, this U-Boot is booted from spi flash ***
U-Boot 2018.01-rc2-00032-gf67dd47-dirty (Dec 21 2017 - 13:56:03 +0800)
DRAM: 1 GiB
MMC: mmc@f0e00000: 0
SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB
In: serial@f0300000
Out: serial@f0300000
Err: serial@f0300000
Net:
Warning: mac@e0100000 (eth0) using random MAC address - ee:4c:58:29:32:f5
eth0: mac@e0100000
RISC-V #
TODO
====================
Boot bbl and riscv-linux
......@@ -58,6 +58,7 @@ Design Notes on Exporting U-Boot Functions to Standalone Applications:
Blackfin 0x00001000 0x00001000
NDS32 0x00300000 0x00300000
Nios II 0x02000000 0x02000000
RISC-V 0x00600000 0x00600000
For example, the "hello world" application may be loaded and
executed on a PowerPC board with the following commands:
......
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