Commit 49ad4029 authored by Derald D. Woods's avatar Derald D. Woods Committed by Tom Rini

ARM: at91: Convert SPL_GENERATE_ATMEL_PMECC_HEADER to Kconfig

This commit converts the following items to Kconfig:

CONFIG_ATMEL_NAND_HWECC
CONFIG_ATMEL_NAND_HW_PMECC
CONFIG_PMECC_CAP
CONFIG_PMECC_SECTOR_SIZE
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER

[PMECC References]
https://www.at91.com/linux4sam/bin/view/Linux4SAM/PmeccConfigure
https://www.at91.com/linux4sam/bin/view/Linux4SAM/AT91Bootstrap

[Mailing List Thread]
https://lists.denx.de/pipermail/u-boot/2018-December/350666.html

Fixes: 5541543f ("configs: at91: Remove CONFIG_SYS_EXTRA_OPTIONS assignment")
[trini: Make the migration be size neutral and possibly not fix the
above in all cases]
Reported-by: default avatarDaniel Evans <photonthunder@gmail.com>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Signed-off-by: default avatarDerald D. Woods <woods.technical@gmail.com>
Signed-off-by: Tom Rini's avatarTom Rini <trini@konsulko.com>
parent 2acc24fc
...@@ -41,6 +41,7 @@ CONFIG_DM_MMC=y ...@@ -41,6 +41,7 @@ CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y CONFIG_NAND=y
CONFIG_NAND_ATMEL=y CONFIG_NAND_ATMEL=y
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_ATMEL=y
......
...@@ -40,6 +40,7 @@ CONFIG_AT91_GPIO=y ...@@ -40,6 +40,7 @@ CONFIG_AT91_GPIO=y
CONFIG_DM_MMC=y CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND_ATMEL=y CONFIG_NAND_ATMEL=y
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_ATMEL=y
......
...@@ -41,6 +41,7 @@ CONFIG_DM_MMC=y ...@@ -41,6 +41,7 @@ CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y CONFIG_NAND=y
CONFIG_NAND_ATMEL=y CONFIG_NAND_ATMEL=y
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_ATMEL=y
......
...@@ -43,6 +43,7 @@ CONFIG_DM_MMC=y ...@@ -43,6 +43,7 @@ CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y CONFIG_NAND=y
CONFIG_NAND_ATMEL=y CONFIG_NAND_ATMEL=y
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_ATMEL=y
......
...@@ -43,6 +43,7 @@ CONFIG_DM_MMC=y ...@@ -43,6 +43,7 @@ CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y CONFIG_NAND=y
CONFIG_NAND_ATMEL=y CONFIG_NAND_ATMEL=y
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_ATMEL=y
......
...@@ -42,6 +42,7 @@ CONFIG_AT91_GPIO=y ...@@ -42,6 +42,7 @@ CONFIG_AT91_GPIO=y
CONFIG_DM_MMC=y CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND_ATMEL=y CONFIG_NAND_ATMEL=y
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_ATMEL=y
......
...@@ -43,6 +43,7 @@ CONFIG_DM_MMC=y ...@@ -43,6 +43,7 @@ CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y CONFIG_NAND=y
CONFIG_NAND_ATMEL=y CONFIG_NAND_ATMEL=y
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_ATMEL=y
......
...@@ -27,6 +27,7 @@ CONFIG_DEFAULT_DEVICE_TREE="at91sam9g45-gurnard" ...@@ -27,6 +27,7 @@ CONFIG_DEFAULT_DEVICE_TREE="at91sam9g45-gurnard"
CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_IS_IN_NAND=y
CONFIG_NAND=y CONFIG_NAND=y
CONFIG_NAND_ATMEL=y CONFIG_NAND_ATMEL=y
CONFIG_ATMEL_NAND_HWECC=y
CONFIG_PHYLIB=y CONFIG_PHYLIB=y
CONFIG_TIMER=y CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y CONFIG_ATMEL_PIT_TIMER=y
......
...@@ -50,6 +50,7 @@ CONFIG_MMC_SDHCI=y ...@@ -50,6 +50,7 @@ CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ATMEL=y CONFIG_MMC_SDHCI_ATMEL=y
CONFIG_NAND=y CONFIG_NAND=y
CONFIG_NAND_ATMEL=y CONFIG_NAND_ATMEL=y
CONFIG_ATMEL_NAND_HW_PMECC=y
CONFIG_DM_ETH=y CONFIG_DM_ETH=y
CONFIG_MACB=y CONFIG_MACB=y
CONFIG_PINCTRL=y CONFIG_PINCTRL=y
......
...@@ -49,6 +49,7 @@ CONFIG_DM_MMC=y ...@@ -49,6 +49,7 @@ CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ATMEL=y CONFIG_MMC_SDHCI_ATMEL=y
CONFIG_NAND_ATMEL=y CONFIG_NAND_ATMEL=y
CONFIG_ATMEL_NAND_HW_PMECC=y
CONFIG_DM_ETH=y CONFIG_DM_ETH=y
CONFIG_MACB=y CONFIG_MACB=y
CONFIG_PINCTRL=y CONFIG_PINCTRL=y
......
...@@ -43,6 +43,7 @@ CONFIG_DM_MMC=y ...@@ -43,6 +43,7 @@ CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y CONFIG_NAND=y
CONFIG_NAND_ATMEL=y CONFIG_NAND_ATMEL=y
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_ATMEL=y
......
...@@ -42,6 +42,7 @@ CONFIG_AT91_GPIO=y ...@@ -42,6 +42,7 @@ CONFIG_AT91_GPIO=y
CONFIG_DM_MMC=y CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND_ATMEL=y CONFIG_NAND_ATMEL=y
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_ATMEL=y
......
...@@ -43,6 +43,7 @@ CONFIG_DM_MMC=y ...@@ -43,6 +43,7 @@ CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y CONFIG_NAND=y
CONFIG_NAND_ATMEL=y CONFIG_NAND_ATMEL=y
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_ATMEL=y
......
...@@ -60,6 +60,7 @@ CONFIG_DM_MMC=y ...@@ -60,6 +60,7 @@ CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y CONFIG_NAND=y
CONFIG_NAND_ATMEL=y CONFIG_NAND_ATMEL=y
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_ETH=y CONFIG_DM_ETH=y
CONFIG_MACB=y CONFIG_MACB=y
CONFIG_PINCTRL=y CONFIG_PINCTRL=y
......
...@@ -56,6 +56,8 @@ CONFIG_AT91_GPIO=y ...@@ -56,6 +56,8 @@ CONFIG_AT91_GPIO=y
CONFIG_DM_MMC=y CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND_ATMEL=y CONFIG_NAND_ATMEL=y
CONFIG_PMECC_CAP=4
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_ETH=y CONFIG_DM_ETH=y
CONFIG_MACB=y CONFIG_MACB=y
CONFIG_PINCTRL=y CONFIG_PINCTRL=y
......
...@@ -67,6 +67,8 @@ CONFIG_SYS_FLASH_PROTECTION=y ...@@ -67,6 +67,8 @@ CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_FLASH_CFI=y
CONFIG_NAND=y CONFIG_NAND=y
CONFIG_NAND_ATMEL=y CONFIG_NAND_ATMEL=y
CONFIG_PMECC_CAP=4
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_ATMEL=y
......
...@@ -61,6 +61,8 @@ CONFIG_FLASH_CFI_DRIVER=y ...@@ -61,6 +61,8 @@ CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_FLASH_CFI=y
CONFIG_NAND_ATMEL=y CONFIG_NAND_ATMEL=y
CONFIG_PMECC_CAP=4
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_ATMEL=y
......
...@@ -62,6 +62,8 @@ CONFIG_SYS_FLASH_PROTECTION=y ...@@ -62,6 +62,8 @@ CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_FLASH_CFI=y
CONFIG_NAND=y CONFIG_NAND=y
CONFIG_NAND_ATMEL=y CONFIG_NAND_ATMEL=y
CONFIG_PMECC_CAP=4
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_ATMEL=y
......
...@@ -58,6 +58,7 @@ CONFIG_DM_MMC=y ...@@ -58,6 +58,7 @@ CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y CONFIG_NAND=y
CONFIG_NAND_ATMEL=y CONFIG_NAND_ATMEL=y
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_ATMEL=y
......
...@@ -54,6 +54,8 @@ CONFIG_I2C_EEPROM=y ...@@ -54,6 +54,8 @@ CONFIG_I2C_EEPROM=y
CONFIG_DM_MMC=y CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND_ATMEL=y CONFIG_NAND_ATMEL=y
CONFIG_PMECC_CAP=8
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_ATMEL=y
......
...@@ -58,6 +58,8 @@ CONFIG_DM_MMC=y ...@@ -58,6 +58,8 @@ CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y CONFIG_NAND=y
CONFIG_NAND_ATMEL=y CONFIG_NAND_ATMEL=y
CONFIG_PMECC_CAP=8
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_ATMEL=y
......
...@@ -58,6 +58,7 @@ CONFIG_DM_MMC=y ...@@ -58,6 +58,7 @@ CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y CONFIG_NAND=y
CONFIG_NAND_ATMEL=y CONFIG_NAND_ATMEL=y
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_ATMEL=y
......
...@@ -54,6 +54,8 @@ CONFIG_AT91_GPIO=y ...@@ -54,6 +54,8 @@ CONFIG_AT91_GPIO=y
CONFIG_DM_MMC=y CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND_ATMEL=y CONFIG_NAND_ATMEL=y
CONFIG_PMECC_CAP=8
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_ATMEL=y
......
...@@ -55,6 +55,8 @@ CONFIG_DM_MMC=y ...@@ -55,6 +55,8 @@ CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_NAND=y CONFIG_NAND=y
CONFIG_NAND_ATMEL=y CONFIG_NAND_ATMEL=y
CONFIG_PMECC_CAP=8
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_DM_SPI_FLASH=y CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_ATMEL=y
......
...@@ -28,5 +28,7 @@ CONFIG_CMD_MTDPARTS=y ...@@ -28,5 +28,7 @@ CONFIG_CMD_MTDPARTS=y
CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_IS_IN_NAND=y
CONFIG_NAND=y CONFIG_NAND=y
CONFIG_NAND_ATMEL=y CONFIG_NAND_ATMEL=y
CONFIG_PMECC_CAP=4
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_LZMA=y CONFIG_LZMA=y
CONFIG_OF_LIBFDT=y CONFIG_OF_LIBFDT=y
...@@ -27,6 +27,8 @@ CONFIG_ENV_IS_IN_NAND=y ...@@ -27,6 +27,8 @@ CONFIG_ENV_IS_IN_NAND=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_NAND=y CONFIG_NAND=y
CONFIG_NAND_ATMEL=y CONFIG_NAND_ATMEL=y
CONFIG_PMECC_CAP=8
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_PHYLIB=y CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_PHY_MICREL_KSZ90X1=y
......
...@@ -20,13 +20,12 @@ To use PMECC in this driver, the user needs to set: ...@@ -20,13 +20,12 @@ To use PMECC in this driver, the user needs to set:
2. The PMECC sector size: CONFIG_PMECC_SECTOR_SIZE. 2. The PMECC sector size: CONFIG_PMECC_SECTOR_SIZE.
It only can be 512 or 1024. It only can be 512 or 1024.
Take AT91SAM9X5EK as an example, the board definition file likes: Take 'configs/at91sam9x5ek_nandflash_defconfig' as an example, the board
configuration file has the following entries:
/* PMECC & PMERRLOC */ CONFIG_PMECC_CAP=2
#define CONFIG_ATMEL_NAND_HWECC 1 CONFIG_PMECC_SECTOR_SIZE=512
#define CONFIG_ATMEL_NAND_HW_PMECC 1 CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
#define CONFIG_PMECC_CAP 2
#define CONFIG_PMECC_SECTOR_SIZE 512
How to enable PMECC header for direct programmable boot.bin How to enable PMECC header for direct programmable boot.bin
----------------------------------------------------------- -----------------------------------------------------------
...@@ -40,7 +39,7 @@ sama5d3 SoC spec (as of 03. April 2014) defines how this PMECC header has to ...@@ -40,7 +39,7 @@ sama5d3 SoC spec (as of 03. April 2014) defines how this PMECC header has to
look like. In order to do so we have a new image type added to mkimage to look like. In order to do so we have a new image type added to mkimage to
generate this PMECC header and integrated this into the build process of SPL. generate this PMECC header and integrated this into the build process of SPL.
To enable the generation of atmel PMECC header for SPL one need to define To enable the generation of atmel PMECC header for SPL one needs to define
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER. The required parameters are taken from CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER. The required parameters are taken from
board configuration and compiled into the host tools atmel_pmecc_params. This board configuration and compiled into the host tools atmel_pmecc_params. This
tool will be called in build process to parametrize mkimage for atmelimage tool will be called in build process to parametrize mkimage for atmelimage
......
...@@ -22,6 +22,44 @@ config NAND_ATMEL ...@@ -22,6 +22,44 @@ config NAND_ATMEL
Enable this driver for NAND flash platforms using an Atmel NAND Enable this driver for NAND flash platforms using an Atmel NAND
controller. controller.
if NAND_ATMEL
config ATMEL_NAND_HWECC
bool "Atmel Hardware ECC"
default n
config ATMEL_NAND_HW_PMECC
bool "Atmel Programmable Multibit ECC (PMECC)"
select ATMEL_NAND_HWECC
default n
help
The Programmable Multibit ECC (PMECC) controller is a programmable
binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder.
config PMECC_CAP
int "PMECC Correctable ECC Bits"
depends on ATMEL_NAND_HW_PMECC
default 2
help
Correctable ECC bits, can be 2, 4, 8, 12, and 24.
config PMECC_SECTOR_SIZE
int "PMECC Sector Size"
depends on ATMEL_NAND_HW_PMECC
default 512
help
Sector size, in bytes, can be 512 or 1024.
config SPL_GENERATE_ATMEL_PMECC_HEADER
bool "Atmel PMECC Header Generation"
select ATMEL_NAND_HWECC
select ATMEL_NAND_HW_PMECC
default n
help
Generate Programmable Multibit ECC (PMECC) header for SPL image.
endif
config NAND_DAVINCI config NAND_DAVINCI
bool "Support TI Davinci NAND controller" bool "Support TI Davinci NAND controller"
help help
......
...@@ -59,12 +59,6 @@ ...@@ -59,12 +59,6 @@
#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PD(5) #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PD(5)
#endif #endif
/* PMECC & PMERRLOC */
#define CONFIG_ATMEL_NAND_HWECC
#define CONFIG_ATMEL_NAND_HW_PMECC
#define CONFIG_PMECC_CAP 2
#define CONFIG_PMECC_SECTOR_SIZE 512
#define CONFIG_EXTRA_ENV_SETTINGS \ #define CONFIG_EXTRA_ENV_SETTINGS \
"console=console=ttyS0,115200\0" \ "console=console=ttyS0,115200\0" \
"mtdparts="CONFIG_MTDPARTS_DEFAULT"\0" \ "mtdparts="CONFIG_MTDPARTS_DEFAULT"\0" \
...@@ -177,6 +171,5 @@ ...@@ -177,6 +171,5 @@
#define CONFIG_SYS_NAND_OOBSIZE 64 #define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
#endif #endif
...@@ -55,12 +55,6 @@ ...@@ -55,12 +55,6 @@
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
#endif #endif
/* PMECC & PMERRLOC */
#define CONFIG_ATMEL_NAND_HWECC 1
#define CONFIG_ATMEL_NAND_HW_PMECC 1
#define CONFIG_PMECC_CAP 2
#define CONFIG_PMECC_SECTOR_SIZE 512
/* USB */ /* USB */
#ifdef CONFIG_CMD_USB #ifdef CONFIG_CMD_USB
#ifndef CONFIG_USB_EHCI_HCD #ifndef CONFIG_USB_EHCI_HCD
...@@ -151,6 +145,5 @@ ...@@ -151,6 +145,5 @@
#define CONFIG_SYS_NAND_OOBSIZE 64 #define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
#endif #endif
...@@ -33,9 +33,6 @@ ...@@ -33,9 +33,6 @@
/* our CLE is AD22 */ /* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE BIT(22) #define CONFIG_SYS_NAND_MASK_CLE BIT(22)
#define CONFIG_SYS_NAND_ONFI_DETECTION #define CONFIG_SYS_NAND_ONFI_DETECTION
/* PMECC & PMERRLOC */
#define CONFIG_ATMEL_NAND_HWECC
#define CONFIG_ATMEL_NAND_HW_PMECC
#endif #endif
#endif /* __CONFIG_H */ #endif /* __CONFIG_H */
...@@ -43,14 +43,8 @@ ...@@ -43,14 +43,8 @@
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ONFI_DETECTION #define CONFIG_SYS_NAND_ONFI_DETECTION
#endif #endif
/* PMECC & PMERRLOC */
#define CONFIG_ATMEL_NAND_HWECC
#define CONFIG_ATMEL_NAND_HW_PMECC
#define CONFIG_PMECC_CAP 4
#define CONFIG_PMECC_SECTOR_SIZE 512
/* USB */ /* USB */
#ifdef CONFIG_CMD_USB #ifdef CONFIG_CMD_USB
#define CONFIG_USB_ATMEL #define CONFIG_USB_ATMEL
#define CONFIG_USB_ATMEL_CLK_SEL_UPLL #define CONFIG_USB_ATMEL_CLK_SEL_UPLL
...@@ -88,6 +82,5 @@ ...@@ -88,6 +82,5 @@
#define CONFIG_SYS_NAND_OOBSIZE 64 #define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
#endif #endif
...@@ -62,14 +62,8 @@ ...@@ -62,14 +62,8 @@
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ONFI_DETECTION #define CONFIG_SYS_NAND_ONFI_DETECTION
#endif #endif
/* PMECC & PMERRLOC */
#define CONFIG_ATMEL_NAND_HWECC
#define CONFIG_ATMEL_NAND_HW_PMECC
#define CONFIG_PMECC_CAP 4
#define CONFIG_PMECC_SECTOR_SIZE 512
/* USB */ /* USB */
#ifdef CONFIG_CMD_USB #ifdef CONFIG_CMD_USB
#define CONFIG_USB_ATMEL_CLK_SEL_UPLL #define CONFIG_USB_ATMEL_CLK_SEL_UPLL
#define CONFIG_USB_OHCI_NEW #define CONFIG_USB_OHCI_NEW
...@@ -109,6 +103,5 @@ ...@@ -109,6 +103,5 @@
#define CONFIG_SYS_NAND_OOBSIZE 64 #define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
#endif #endif
...@@ -37,9 +37,6 @@ ...@@ -37,9 +37,6 @@
/* our CLE is AD22 */ /* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ONFI_DETECTION #define CONFIG_SYS_NAND_ONFI_DETECTION
/* PMECC & PMERRLOC */
#define CONFIG_ATMEL_NAND_HWECC
#define CONFIG_ATMEL_NAND_HW_PMECC
#endif #endif
/* SPL */ /* SPL */
...@@ -64,8 +61,6 @@ ...@@ -64,8 +61,6 @@
#define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE #define CONFIG_SPL_NAND_BASE
#endif #endif
#define CONFIG_PMECC_CAP 8
#define CONFIG_PMECC_SECTOR_SIZE 512
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE 0x1000 #define CONFIG_SYS_NAND_PAGE_SIZE 0x1000
...@@ -73,6 +68,5 @@ ...@@ -73,6 +68,5 @@
#define CONFIG_SYS_NAND_OOBSIZE 224 #define CONFIG_SYS_NAND_OOBSIZE 224
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
#endif #endif
...@@ -37,9 +37,6 @@ ...@@ -37,9 +37,6 @@
/* our CLE is AD22 */ /* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ONFI_DETECTION #define CONFIG_SYS_NAND_ONFI_DETECTION
/* PMECC & PMERRLOC */
#define CONFIG_ATMEL_NAND_HWECC
#define CONFIG_ATMEL_NAND_HW_PMECC
#endif #endif
/* SPL */ /* SPL */
...@@ -63,8 +60,6 @@ ...@@ -63,8 +60,6 @@
#define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE #define CONFIG_SPL_NAND_BASE
#endif #endif
#define CONFIG_PMECC_CAP 8
#define CONFIG_PMECC_SECTOR_SIZE 512
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE 0x1000 #define CONFIG_SYS_NAND_PAGE_SIZE 0x1000
...@@ -72,6 +67,5 @@ ...@@ -72,6 +67,5 @@
#define CONFIG_SYS_NAND_OOBSIZE 224 #define CONFIG_SYS_NAND_OOBSIZE 224
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER