Commit 63b2316c authored by Ashish Kumar's avatar Ashish Kumar Committed by York Sun

fsl-layerscape: Consolidate registers space defination for CCI-400 bus

CoreLink Cache Coherent Interconnect (CCI) provides full cache
coherency between two clusters of multi-core CPUs and I/O coherency
for devices and I/O masters.

This patch add new config option SYS_FSL_HAS_CCI400 and moves
existing register space definaton of CCI-400 bus to fsl_immap to be
shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET
in Kconfig.
Signed-off-by: default avatarAshish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Prabhakar Kushwaha's avatarPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
[YS: revised commit message, squashed patches for armv8 and armv7]
Reviewed-by: default avatarYork Sun <york.sun@nxp.com>
parent 584f316f
......@@ -312,6 +312,15 @@ Many of the options are named exactly as the corresponding Linux
kernel configuration options. The intention is to make it easier to
build a config tool - later.
- ARM Platform Bus Type(CCI):
CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which
provides full cache coherency between two clusters of multi-core
CPUs and I/O coherency for devices and I/O masters
CONFIG_SYS_FSL_HAS_CCI400
Defined For SoC that has cache coherent interconnect
CCN-400
The following options need to be configured:
......
......@@ -5,6 +5,7 @@ config ARCH_LS1021A
select SYS_FSL_ERRATUM_A009663
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_HAS_CCI400
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE if SYS_FSL_DDR
......@@ -49,9 +50,20 @@ config SECURE_BOOT
Enable Freescale Secure Boot feature. Normally selected
by defconfig. If unsure, do not change.
config SYS_CCI400_OFFSET
hex "Offset for CCI400 base"
depends on SYS_FSL_HAS_CCI400
default 0x180000
help
Offset for CCI400 base.
CCI400 base addr = CCSRBAR + CCI400_OFFSET
config SYS_FSL_ERRATUM_A010315
bool "Workaround for PCIe erratum A010315"
config SYS_FSL_HAS_CCI400
bool
config SYS_FSL_SRDS_1
bool
......
......@@ -80,7 +80,8 @@ void erratum_a010315(void)
int arch_soc_init(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
unsigned int major;
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
......
......@@ -85,6 +85,7 @@ config ARCH_LS2080A
config FSL_LSCH2
bool
select SYS_FSL_HAS_CCI400
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SEC_BE
......@@ -248,6 +249,15 @@ config QSPI_AHB_INIT
But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
bus for those flashes to support the full QSPI flash size.
config SYS_CCI400_OFFSET
hex "Offset for CCI400 base"
depends on SYS_FSL_HAS_CCI400
default 0x3090000 if ARCH_LS1088A
default 0x180000 if FSL_LSCH2
help
Offset for CCI400 base
CCI400 base addr = CCSRBAR + CCI400_OFFSET
config SYS_FSL_IFC_BANK_COUNT
int "Maximum banks of Integrated flash controller"
depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
......@@ -255,6 +265,9 @@ config SYS_FSL_IFC_BANK_COUNT
default 4 if ARCH_LS1046A
default 8 if ARCH_LS2080A
config SYS_FSL_HAS_CCI400
bool
config SYS_FSL_HAS_DP_DDR
bool
......
......@@ -16,6 +16,7 @@
#include <asm/arch/soc.h>
#include <asm/arch/cpu.h>
#include <asm/arch/speed.h>
#include <fsl_immap.h>
#include <asm/arch/mp.h>
#include <efi_loader.h>
#include <fm_eth.h>
......
......@@ -5,6 +5,7 @@
*/
#include <common.h>
#include <fsl_immap.h>
#include <fsl_ifc.h>
#include <ahci.h>
#include <scsi.h>
......@@ -285,7 +286,8 @@ static void erratum_a008850_early(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
/* part 1 of 2 */
struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
/* Skip if running at lower exception level */
......@@ -304,7 +306,8 @@ void erratum_a008850_post(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
/* part 2 of 2 */
struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
u32 tmp;
......@@ -439,7 +442,8 @@ int setup_chip_volt(void)
void fsl_lsch2_early_init_f(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
......
......@@ -15,7 +15,6 @@
#define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040)
#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)
#define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000)
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
#define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000)
......@@ -544,54 +543,6 @@ struct ccsr_serdes {
u8 res_19a0[0x2000-0x19a0]; /* from 0x19a0 to 0x1fff */
};
#define CCI400_CTRLORD_TERM_BARRIER 0x00000008
#define CCI400_CTRLORD_EN_BARRIER 0
#define CCI400_SHAORD_NON_SHAREABLE 0x00000002
#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002
#define CCI400_SNOOP_REQ_EN 0x00000001
/* CCI-400 registers */
struct ccsr_cci400 {
u32 ctrl_ord; /* Control Override */
u32 spec_ctrl; /* Speculation Control */
u32 secure_access; /* Secure Access */
u32 status; /* Status */
u32 impr_err; /* Imprecise Error */
u8 res_14[0x100 - 0x14];
u32 pmcr; /* Performance Monitor Control */
u8 res_104[0xfd0 - 0x104];
u32 pid[8]; /* Peripheral ID */
u32 cid[4]; /* Component ID */
struct {
u32 snoop_ctrl; /* Snoop Control */
u32 sha_ord; /* Shareable Override */
u8 res_1008[0x1100 - 0x1008];
u32 rc_qos_ord; /* read channel QoS Value Override */
u32 wc_qos_ord; /* read channel QoS Value Override */
u8 res_1108[0x110c - 0x1108];
u32 qos_ctrl; /* QoS Control */
u32 max_ot; /* Max OT */
u8 res_1114[0x1130 - 0x1114];
u32 target_lat; /* Target Latency */
u32 latency_regu; /* Latency Regulation */
u32 qos_range; /* QoS Range */
u8 res_113c[0x2000 - 0x113c];
} slave[5]; /* Slave Interface */
u8 res_6000[0x9004 - 0x6000];
u32 cycle_counter; /* Cycle counter */
u32 count_ctrl; /* Count Control */
u32 overflow_status; /* Overflow Flag Status */
u8 res_9010[0xa000 - 0x9010];
struct {
u32 event_select; /* Event Select */
u32 event_count; /* Event Count */
u32 counter_ctrl; /* Counter Control */
u32 overflow_status; /* Overflow Flag Status */
u8 res_a010[0xb000 - 0xa010];
} pcounter[4]; /* Performance Counter */
u8 res_e004[0x10000 - 0xe004];
};
/* MMU 500 */
#define SMMU_SCR0 (SMMU_BASE + 0x0)
#define SMMU_SCR1 (SMMU_BASE + 0x4)
......
......@@ -20,7 +20,6 @@
#define SYS_FSL_GIC_ADDR (CONFIG_SYS_IMMR + 0x00400000)
#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)
#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
......
......@@ -6,6 +6,7 @@
#ifndef __ASM_ARCH_LS102XA_IMMAP_H_
#define __ASM_ARCH_LS102XA_IMMAP_H_
#include <fsl_immap.h>
#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
......@@ -374,53 +375,7 @@ struct ccsr_serdes {
u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */
};
#define CCI400_CTRLORD_TERM_BARRIER 0x00000008
#define CCI400_CTRLORD_EN_BARRIER 0
#define CCI400_SHAORD_NON_SHAREABLE 0x00000002
#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002
#define CCI400_SNOOP_REQ_EN 0x00000001
/* CCI-400 registers */
struct ccsr_cci400 {
u32 ctrl_ord; /* Control Override */
u32 spec_ctrl; /* Speculation Control */
u32 secure_access; /* Secure Access */
u32 status; /* Status */
u32 impr_err; /* Imprecise Error */
u8 res_14[0x100 - 0x14];
u32 pmcr; /* Performance Monitor Control */
u8 res_104[0xfd0 - 0x104];
u32 pid[8]; /* Peripheral ID */
u32 cid[4]; /* Component ID */
struct {
u32 snoop_ctrl; /* Snoop Control */
u32 sha_ord; /* Shareable Override */
u8 res_1008[0x1100 - 0x1008];
u32 rc_qos_ord; /* read channel QoS Value Override */
u32 wc_qos_ord; /* read channel QoS Value Override */
u8 res_1108[0x110c - 0x1108];
u32 qos_ctrl; /* QoS Control */
u32 max_ot; /* Max OT */
u8 res_1114[0x1130 - 0x1114];
u32 target_lat; /* Target Latency */
u32 latency_regu; /* Latency Regulation */
u32 qos_range; /* QoS Range */
u8 res_113c[0x2000 - 0x113c];
} slave[5]; /* Slave Interface */
u8 res_6000[0x9004 - 0x6000];
u32 cycle_counter; /* Cycle counter */
u32 count_ctrl; /* Count Control */
u32 overflow_status; /* Overflow Flag Status */
u8 res_9010[0xa000 - 0x9010];
struct {
u32 event_select; /* Event Select */
u32 event_count; /* Event Count */
u32 counter_ctrl; /* Counter Control */
u32 overflow_status; /* Overflow Flag Status */
u8 res_a010[0xb000 - 0xa010];
} pcounter[4]; /* Performance Counter */
u8 res_e004[0x10000 - 0xe004];
};
/* AHCI (sata) register map */
struct ccsr_ahci {
......
......@@ -71,7 +71,9 @@ int board_early_init_f(void)
int board_init(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
/*
* Set CCI-400 control override register to enable barrier
* transaction
......
......@@ -106,8 +106,8 @@ int misc_init_r(void)
int board_init(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
CONFIG_SYS_CCI400_ADDR;
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
/* Set CCI-400 control override register to enable barrier
* transaction */
......
......@@ -104,7 +104,8 @@ int board_early_init_f(void)
int board_init(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
/*
* Set CCI-400 control override register to enable barrier
* transaction
......
......@@ -204,7 +204,8 @@ int board_early_init_f(void)
#ifdef CONFIG_SPL_BUILD
void board_init_f(ulong dummy)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
unsigned int major;
#ifdef CONFIG_NAND_BOOT
......@@ -425,7 +426,8 @@ int misc_init_r(void)
int board_init(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
unsigned int major;
#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
......@@ -460,7 +462,8 @@ int board_init(void)
#if defined(CONFIG_DEEP_SLEEP)
void board_sleep_prepare(void)
{
struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
unsigned int major;
major = get_soc_major_rev();
......
......@@ -133,4 +133,55 @@ struct ccsr_ddr {
u8 res_e5c[164];
u32 debug[64]; /* debug_1 to debug_64 */
};
#ifdef CONFIG_SYS_FSL_HAS_CCI400
#define CCI400_CTRLORD_TERM_BARRIER 0x00000008
#define CCI400_CTRLORD_EN_BARRIER 0
#define CCI400_SHAORD_NON_SHAREABLE 0x00000002
#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002
#define CCI400_SNOOP_REQ_EN 0x00000001
/* CCI-400 registers */
struct ccsr_cci400 {
u32 ctrl_ord; /* Control Override */
u32 spec_ctrl; /* Speculation Control */
u32 secure_access; /* Secure Access */
u32 status; /* Status */
u32 impr_err; /* Imprecise Error */
u8 res_14[0x100 - 0x14];
u32 pmcr; /* Performance Monitor Control */
u8 res_104[0xfd0 - 0x104];
u32 pid[8]; /* Peripheral ID */
u32 cid[4]; /* Component ID */
struct {
u32 snoop_ctrl; /* Snoop Control */
u32 sha_ord; /* Shareable Override */
u8 res_1008[0x1100 - 0x1008];
u32 rc_qos_ord; /* read channel QoS Value Override */
u32 wc_qos_ord; /* read channel QoS Value Override */
u8 res_1108[0x110c - 0x1108];
u32 qos_ctrl; /* QoS Control */
u32 max_ot; /* Max OT */
u8 res_1114[0x1130 - 0x1114];
u32 target_lat; /* Target Latency */
u32 latency_regu; /* Latency Regulation */
u32 qos_range; /* QoS Range */
u8 res_113c[0x2000 - 0x113c];
} slave[5]; /* Slave Interface */
u8 res_6000[0x9004 - 0x6000];
u32 cycle_counter; /* Cycle counter */
u32 count_ctrl; /* Count Control */
u32 overflow_status; /* Overflow Flag Status */
u8 res_9010[0xa000 - 0x9010];
struct {
u32 event_select; /* Event Select */
u32 event_count; /* Event Count */
u32 counter_ctrl; /* Counter Control */
u32 overflow_status; /* Overflow Flag Status */
u8 res_a010[0xb000 - 0xa010];
} pcounter[4]; /* Performance Counter */
u8 res_e004[0x10000 - 0xe004];
};
#endif
#endif /* __FSL_IMMAP_H */
......@@ -2435,7 +2435,6 @@ CONFIG_SYS_CACHE_STASHING
CONFIG_SYS_CADMUS_BASE_REG
CONFIG_SYS_CBSIZE
CONFIG_SYS_CCCR
CONFIG_SYS_CCI400_ADDR
CONFIG_SYS_CCSRBAR
CONFIG_SYS_CCSRBAR_PHYS
CONFIG_SYS_CCSRBAR_PHYS_HIGH
......
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