Commit a85f9f21 authored by wdenk's avatar wdenk

Patch by Steven Scholz, 06 Apr 2005:

- creating SoC subdir for Atmel AT91RM9200 cpu/arm920t/at91rm9200
- moving code out of cpu/at91rm9200 into cpu/arm920t/at91rm9200
parent 20787e23
......@@ -2,6 +2,10 @@
Changes for U-Boot 1.1.3:
======================================================================
* Patch by Steven Scholz, 06 Apr 2005:
- creating SoC subdir for Atmel AT91RM9200 cpu/arm920t/at91rm9200
- moving code out of cpu/at91rm9200 into cpu/arm920t/at91rm9200
* Patches by Robert Whaley, 29 Nov 2004:
- update the pxa-regs.h file for PXA27x chips
- add PXA27x based ADSVIX board
......
......@@ -1285,6 +1285,12 @@ xtract_omap1610xxx = $(subst _cs0boot,,$(subst _cs3boot,,$(subst _cs_autoboot,,$
xtract_omap730p2 = $(subst _cs0boot,,$(subst _cs3boot,, $(subst _config,,$1)))
at91rm9200dk_config : unconfig
@./mkconfig $(@:_config=) arm arm920t at91rm9200dk NULL at91rm9200
cmc_pu2_config : unconfig
@./mkconfig $(@:_config=) arm arm920t cmc_pu2 NULL at91rm9200
integratorap_config : unconfig
@./mkconfig $(@:_config=) arm arm926ejs integratorap
......@@ -1418,16 +1424,6 @@ modnet50_config : unconfig
evb4510_config : unconfig
@./mkconfig $(@:_config=) arm arm720t evb4510
#########################################################################
## AT91RM9200 Systems
#########################################################################
at91rm9200dk_config : unconfig
@./mkconfig $(@:_config=) arm at91rm9200 at91rm9200dk
cmc_pu2_config : unconfig
@./mkconfig $(@:_config=) arm at91rm9200 cmc_pu2
#########################################################################
## XScale Systems
#########################################################################
......
......@@ -126,12 +126,12 @@ Directory Hierarchy:
- 74xx_7xx Files specific to Freescale MPC74xx and 7xx CPUs
- arm720t Files specific to ARM 720 CPUs
- arm920t Files specific to ARM 920 CPUs
- at91rm9200 Files specific to Atmel AT91RM9200 CPU
- imx Files specific to Freescale MC9328 i.MX CPUs
- s3c24x0 Files specific to Samsung S3C24X0 CPUs
- arm925t Files specific to ARM 925 CPUs
- arm926ejs Files specific to ARM 926 CPUs
- arm1136 Files specific to ARM 1136 CPUs
- at91rm9200 Files specific to Atmel AT91RM9200 CPUs
- i386 Files specific to i386 CPUs
- ixp Files specific to Intel XScale IXP CPUs
- mcf52x2 Files specific to Freescale ColdFire MCF52x2 CPUs
......
......@@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS := adsvix.o pcmcia.o
SOBJS := memsetup.o pxavoltage.o
SOBJS := lowlevel_init.o pxavoltage.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
......
......@@ -5,7 +5,7 @@
*
* NOTE: I haven't clean this up considerably, just enough to get it
* running. See hal_platform_setup.h for the source. See
* board/cradle/memsetup.S for another PXA250 setup that is
* board/cradle/lowlevel_init.S for another PXA250 setup that is
* much cleaner.
*
* See file CREDITS for list of people who contributed to this
......@@ -43,8 +43,8 @@
* Memory setup
*/
.globl memsetup
memsetup:
.globl lowlevel_init
lowlevel_init:
/* Set up GPIO pins first ----------------------------------------- */
......@@ -445,7 +445,6 @@ initclks:
str r1, [r0]
/* FIXME */
// #define NODEBUG
#ifdef NODEBUG
/*Disable software and data breakpoints */
mov r0,#0
......@@ -456,13 +455,12 @@ initclks:
/*Enable all debug functionality */
mov r0,#0x80000000
mcr p14,0,r0,c10,c0,0 /* dcsr */
#endif
/* ---------------------------------------------------------------- */
/* End memsetup */
/* End lowlevel_init */
/* ---------------------------------------------------------------- */
endmemsetup:
endlowlevel_init:
mov pc, lr
......@@ -228,4 +228,3 @@ setleds:
bne 1b
mov pc, lr
......@@ -32,7 +32,7 @@ SECTIONS
. = ALIGN(4);
.text :
{
cpu/at91rm9200/start.o (.text)
cpu/arm920t/start.o (.text)
*(.text)
}
......
......@@ -32,7 +32,7 @@ SECTIONS
. = ALIGN(4);
.text :
{
cpu/at91rm9200/start.o (.text)
cpu/arm920t/start.o (.text)
*(.text)
}
......
#
# (C) Copyright 2003
# (C) Copyright 2000-2005
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
......@@ -23,22 +23,20 @@
include $(TOPDIR)/config.mk
LIB = lib$(CPU).a
LIB = lib$(SOC).a
START = start.o
OBJS = serial.o interrupts.o cpu.o \
at91rm9200_ether.o i2c.o
SOBJS = lowlevel.o
OBJS = ether.o i2c.o interrupts.o serial.o
SOBJS = lowlevel_init.o
all: .depend $(START) $(LIB)
all: .depend $(LIB)
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
#########################################################################
.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
.depend: Makefile $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
sinclude .depend
......
......@@ -31,9 +31,9 @@
*/
#include <common.h>
#include <asm/io.h>
/*#include <asm/io.h>*/
#include <asm/arch/hardware.h>
#include <asm/proc/ptrace.h>
/*#include <asm/proc/ptrace.h>*/
/* the number of clocks per CFG_HZ */
#define TIMER_LOAD_VAL (CFG_HZ_CLOCK/CFG_HZ)
......@@ -42,119 +42,11 @@
#define READ_TIMER (tmr->TC_CV & 0x0000ffff)
AT91PS_TC tmr;
#ifdef CONFIG_USE_IRQ
#error There is no IRQ support for AT91RM9200 in U-Boot yet.
#else
void enable_interrupts (void)
{
return;
}
int disable_interrupts (void)
{
return 0;
}
#endif
void bad_mode (void)
{
panic ("Resetting CPU ...\n");
reset_cpu (0);
}
void show_regs (struct pt_regs *regs)
{
unsigned long flags;
const char *processor_modes[] = {
"USER_26", "FIQ_26", "IRQ_26", "SVC_26",
"UK4_26", "UK5_26", "UK6_26", "UK7_26",
"UK8_26", "UK9_26", "UK10_26", "UK11_26",
"UK12_26", "UK13_26", "UK14_26", "UK15_26",
"USER_32", "FIQ_32", "IRQ_32", "SVC_32",
"UK4_32", "UK5_32", "UK6_32", "ABT_32",
"UK8_32", "UK9_32", "UK10_32", "UND_32",
"UK12_32", "UK13_32", "UK14_32", "SYS_32",
};
flags = condition_codes (regs);
printf ("pc : [<%08lx>] lr : [<%08lx>]\n"
"sp : %08lx ip : %08lx fp : %08lx\n",
instruction_pointer (regs),
regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
printf ("r10: %08lx r9 : %08lx r8 : %08lx\n",
regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
printf ("Flags: %c%c%c%c",
flags & CC_N_BIT ? 'N' : 'n',
flags & CC_Z_BIT ? 'Z' : 'z',
flags & CC_C_BIT ? 'C' : 'c',
flags & CC_V_BIT ? 'V' : 'v');
printf (" IRQs %s FIQs %s Mode %s%s\n",
interrupts_enabled (regs) ? "on" : "off",
fast_interrupts_enabled (regs) ? "on" : "off",
processor_modes[processor_mode (regs)],
thumb_mode (regs) ? " (T)" : "");
}
void do_undefined_instruction (struct pt_regs *pt_regs)
{
printf ("undefined instruction\n");
show_regs (pt_regs);
bad_mode ();
}
void do_software_interrupt (struct pt_regs *pt_regs)
{
printf ("software interrupt\n");
show_regs (pt_regs);
bad_mode ();
}
void do_prefetch_abort (struct pt_regs *pt_regs)
{
printf ("prefetch abort\n");
show_regs (pt_regs);
bad_mode ();
}
void do_data_abort (struct pt_regs *pt_regs)
{
printf ("data abort\n");
show_regs (pt_regs);
bad_mode ();
}
void do_not_used (struct pt_regs *pt_regs)
{
printf ("not used\n");
show_regs (pt_regs);
bad_mode ();
}
void do_fiq (struct pt_regs *pt_regs)
{
printf ("fast interrupt request\n");
show_regs (pt_regs);
bad_mode ();
}
void do_irq (struct pt_regs *pt_regs)
{
printf ("interrupt request\n");
show_regs (pt_regs);
bad_mode ();
}
static ulong timestamp;
static ulong lastinc;
int interrupt_init (void)
{
tmr = AT91C_BASE_TC0;
/* enables TC1.0 clock */
......@@ -266,3 +158,53 @@ ulong get_tbclk (void)
tbclk = CFG_HZ;
return tbclk;
}
/*
* Reset the cpu by setting up the watchdog timer and let him time out
* or toggle a GPIO pin on the AT91RM9200DK board
*/
void reset_cpu (ulong ignored)
{
#ifdef CONFIG_DBGU
AT91PS_USART us = (AT91PS_USART) AT91C_BASE_DBGU;
#endif
#ifdef CONFIG_USART0
AT91PS_USART us = AT91C_BASE_US0;
#endif
#ifdef CONFIG_USART1
AT91PS_USART us = AT91C_BASE_US1;
#endif
#ifdef CONFIG_AT91RM9200DK
AT91PS_PIO pio = AT91C_BASE_PIOA;
#endif
/*shutdown the console to avoid strange chars during reset */
us->US_CR = (AT91C_US_RSTRX | AT91C_US_RSTTX);
#ifdef CONFIG_AT91RM9200DK
/* Clear PA19 to trigger the hard reset */
pio->PIO_CODR = 0x00080000;
pio->PIO_OER = 0x00080000;
pio->PIO_PER = 0x00080000;
#endif
/* this is the way Linux does it */
/* FIXME:
* These defines should be moved into
* include/asm-arm/arch-at91rm9200/AT91RM9200.h
* as soon as the whitespace fix gets applied.
*/
#define AT91C_ST_RSTEN (0x1 << 16)
#define AT91C_ST_EXTEN (0x1 << 17)
#define AT91C_ST_WDRST (0x1 << 0)
#define ST_WDMR *((unsigned long *)0xfffffd08) /* watchdog mode register */
#define ST_CR *((unsigned long *)0xfffffd00) /* system clock control register */
ST_WDMR = AT91C_ST_RSTEN | AT91C_ST_EXTEN | 1 ;
ST_CR = AT91C_ST_WDRST;
while (1);
/* Never reached */
}
#
# (C) Copyright 2002
# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
# Marius Groeger <mgroeger@sysgo.de>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
-mshort-load-bytes -msoft-float
PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=arm7tdmi
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* CPU specific code
*/
#include <common.h>
#include <command.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#if !defined(CONFIG_DBGU) && !defined(CONFIG_USART0) && !defined(CONFIG_USART1)
#error must define one of CONFIG_DBGU or CONFIG_USART0 or CONFIG_USART1
#endif
/* read co-processor 15, register #1 (control register) */
static unsigned long read_p15_c1(void)
{
unsigned long value;
__asm__ __volatile__(
"mrc p15, 0, %0, c1, c0, 0 @ read control reg\n"
: "=r" (value)
:
: "memory");
/*printf("p15/c1 is = %08lx\n", value); */
return value;
}
/* write to co-processor 15, register #1 (control register) */
static void write_p15_c1(unsigned long value)
{
/*printf("write %08lx to p15/c1\n", value); */
__asm__ __volatile__(
"mcr p15, 0, %0, c1, c0, 0 @ write it back\n"
: "=r" (value)
:
: "memory");
read_p15_c1();
}
static void cp_delay(void)
{
volatile int i;
/* copro seems to need some delay between reading and writing */
for (i=0; i<100; i++);
}
/* See also ARM Ref. Man. */
#define C1_MMU (1<<0) /* mmu off/on */
#define C1_ALIGN (1<<1) /* alignment faults off/on */
#define C1_IDC (1<<2) /* icache and/or dcache off/on */
#define C1_WRITE_BUFFER (1<<3) /* write buffer off/on */
#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */
#define C1_SYS_PROT (1<<8) /* system protection */
#define C1_ROM_PROT (1<<9) /* ROM protection */
#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */
int cpu_init(void)
{
/*
* setup up stacks if necessary
*/
#ifdef CONFIG_USE_IRQ
DECLARE_GLOBAL_DATA_PTR;
IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
#endif
return 0;
}
int cleanup_before_linux(void)
{
/*
* this function is called just before we call linux
* it prepares the processor for linux
*
* we turn off caches etc ...
* and we set the CPU-speed to 73 MHz - see start.S for details
*/
disable_interrupts();
return 0;
}
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
#ifdef CFG_SOFT_RESET
disable_interrupts();
reset_cpu(0);
#else
#ifdef CONFIG_DBGU
AT91PS_USART us = (AT91PS_USART) AT91C_BASE_DBGU;
#endif
#ifdef CONFIG_USART0
AT91PS_USART us = AT91C_BASE_US0;
#endif
#ifdef CONFIG_USART1
AT91PS_USART us = AT91C_BASE_US1;
#endif
AT91PS_PIO pio = AT91C_BASE_PIOA;
/*shutdown the console to avoid strange chars during reset */
us->US_CR = (AT91C_US_RSTRX | AT91C_US_RSTTX);
#ifdef CONFIG_AT91RM9200DK
/* Clear PA19 to trigger the hard reset */
pio->PIO_CODR = 0x00080000;
pio->PIO_OER = 0x00080000;
pio->PIO_PER = 0x00080000;
#endif
#ifdef CONFIG_CMC_PU2
/* this is the way Linux does it */
#define AT91C_ST_RSTEN (0x1 << 16)
#define AT91C_ST_EXTEN (0x1 << 17)
#define AT91C_ST_WDRST (0x1 << 0)
/* watchdog mode register */
#define ST_WDMR *((unsigned long *)0xfffffd08)
/* system clock control register */
#define ST_CR *((unsigned long *)0xfffffd00)
ST_WDMR = AT91C_ST_RSTEN | AT91C_ST_EXTEN | 1 ;
ST_CR = AT91C_ST_WDRST;
/* Never reached */
#endif
#endif
return 0;
}
void icache_enable(void)
{
ulong reg;
reg = read_p15_c1();
cp_delay();
write_p15_c1(reg | C1_IDC);
}
void icache_disable(void)
{
ulong reg;
reg = read_p15_c1();
cp_delay();
write_p15_c1(reg & ~C1_IDC);
}
int icache_status(void)
{
return (read_p15_c1() & C1_IDC) != 0;
return 0;
}
void dcache_enable(void)
{
ulong reg;
reg = read_p15_c1();
cp_delay();
write_p15_c1(reg | C1_IDC);
}
void dcache_disable(void)
{
ulong reg;
reg = read_p15_c1();
cp_delay();
write_p15_c1(reg & ~C1_IDC);
}
int dcache_status(void)
{
return (read_p15_c1() & C1_IDC) != 0;
return 0;
}
/*
* armboot - Startup Code for ARM720 CPU-core
*
* Copyright (c) 2001 Marius Grger <mag@sysgo.de>
* Copyright (c) 2002 Alex Zpke <azu@sysgo.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include "config.h"
#include "version.h"
/*
*************************************************************************
*
* Jump vector table as in table 3.1 in [1]
*
*************************************************************************
*/
.globl _start
_start: b reset
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
ldr pc, _data_abort
ldr pc, _not_used
ldr pc, _irq
ldr pc, _fiq
_undefined_instruction: .word undefined_instruction
_software_interrupt: .word software_interrupt
_prefetch_abort: .word prefetch_abort
_data_abort: .word data_abort
_not_used: .word not_used
_irq: .word irq
_fiq: .word fiq
.balignl 16,0xdeadbeef
/*
*************************************************************************
*
* Startup Code (reset vector)
*
* do important init only if we don't start from memory!
* relocate armboot to ram
* setup stack
* jump to second stage