Commit aff66f22 authored by Tom Rini's avatar Tom Rini

Merge tag 'mips-pull-2019-01-23' of git://git.denx.de/u-boot-mips

- MIPS: mscc: ocelot: add ethernet switch and network support
- MIPS: mscc: add support for ServalT SoC family
- MIPS: mscc: add support for Serval SoC family
parents 7794fe2c a834cb81
......@@ -539,6 +539,7 @@ F: drivers/gpio/mscc_sgpio.c
F: drivers/spi/mscc_bb_spi.c
F: include/configs/vcoreiii.h
F: drivers/pinctrl/mscc/
F: drivers/net/ocelot_switch.c
MIPS JZ4780
M: Ezequiel Garcia <ezequiel@collabora.com>
......
......@@ -20,6 +20,8 @@ dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb
dtb-$(CONFIG_SOC_LUTON) += luton_pcb090.dtb luton_pcb091.dtb
dtb-$(CONFIG_SOC_OCELOT) += ocelot_pcb120.dtb ocelot_pcb123.dtb
dtb-$(CONFIG_SOC_JR2) += jr2_pcb110.dtb jr2_pcb111.dtb serval2_pcb112.dtb
dtb-$(CONFIG_SOC_SERVALT) += servalt_pcb116.dtb
dtb-$(CONFIG_SOC_SERVAL) += serval_pcb105.dtb serval_pcb106.dtb
targets += $(dtb-y)
......
......@@ -112,6 +112,98 @@
status = "disabled";
};
switch@1010000 {
pinctrl-0 = <&miim1_pins>;
pinctrl-names = "default";
compatible = "mscc,vsc7514-switch";
reg = <0x1010000 0x10000>, /* VTSS_TO_SYS */
<0x1030000 0x10000>, /* VTSS_TO_REW */
<0x1080000 0x100>, /* VTSS_TO_DEVCPU_QS */
<0x10d0000 0x10000>, /* VTSS_TO_HSIO */
<0x11e0000 0x100>, /* VTSS_TO_DEV_0 */
<0x11f0000 0x100>, /* VTSS_TO_DEV_1 */
<0x1200000 0x100>, /* VTSS_TO_DEV_2 */
<0x1210000 0x100>, /* VTSS_TO_DEV_3 */
<0x1220000 0x100>, /* VTSS_TO_DEV_4 */
<0x1230000 0x100>, /* VTSS_TO_DEV_5 */
<0x1240000 0x100>, /* VTSS_TO_DEV_6 */
<0x1250000 0x100>, /* VTSS_TO_DEV_7 */
<0x1260000 0x100>, /* VTSS_TO_DEV_8 */
<0x1270000 0x100>, /* NA */
<0x1280000 0x100>, /* NA */
<0x1800000 0x80000>, /* VTSS_TO_QSYS */
<0x1880000 0x10000>; /* VTSS_TO_ANA */
reg-names = "sys", "rew", "qs", "hsio", "port0",
"port1", "port2", "port3", "port4", "port5",
"port6", "port7", "port8", "port9",
"port10", "qsys", "ana";
interrupts = <21 22>;
interrupt-names = "xtr", "inj";
status = "okay";
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
port0: port@0 {
reg = <0>;
};
port1: port@1 {
reg = <1>;
};
port2: port@2 {
reg = <2>;
};
port3: port@3 {
reg = <3>;
};
port4: port@4 {
reg = <4>;
};
port5: port@5 {
reg = <5>;
};
port6: port@6 {
reg = <6>;
};
port7: port@7 {
reg = <7>;
};
port8: port@8 {
reg = <8>;
};
port9: port@9 {
reg = <9>;
};
port10: port@10 {
reg = <10>;
};
};
};
mdio0: mdio@107009c {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mscc,ocelot-miim";
reg = <0x107009c 0x24>, <0x10700f0 0x8>;
interrupts = <14>;
status = "disabled";
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
phy2: ethernet-phy@2 {
reg = <2>;
};
phy3: ethernet-phy@3 {
reg = <3>;
};
};
reset@1070008 {
compatible = "mscc,ocelot-chip-reset";
reg = <0x1070008 0x4>;
......@@ -144,6 +236,11 @@
function = "si";
};
miim1_pins: miim1-pins {
pins = "GPIO_14", "GPIO_15";
function = "miim1";
};
spi_cs2_pin: spi-cs2-pin {
pins = "GPIO_9";
function = "si";
......
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 Microsemi Corporation
*/
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mscc,serval";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "mips,mips24KEc";
device_type = "cpu";
clocks = <&cpu_clk>;
reg = <0>;
};
};
aliases {
serial0 = &uart0;
};
cpuintc: interrupt-controller@0 {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
compatible = "mti,cpu-interrupt-controller";
};
cpu_clk: cpu-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <416666666>;
};
sys_clk: sys-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <208333333>;
};
ahb_clk: ahb-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <208333333>;
};
ahb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x70000000 0x2000000>;
interrupt-parent = <&intc>;
cpu_ctrl: syscon@0 {
compatible = "mscc,serval-cpu-syscon", "syscon";
reg = <0x0 0x2c>;
};
intc: interrupt-controller@70 {
compatible = "mscc,serval-icpu-intr";
reg = <0x70 0x70>;
#interrupt-cells = <1>;
interrupt-controller;
interrupt-parent = <&cpuintc>;
interrupts = <2>;
};
uart0: serial@100000 {
pinctrl-0 = <&uart_pins>;
pinctrl-names = "default";
compatible = "ns16550a";
reg = <0x100000 0x20>;
interrupts = <6>;
clocks = <&ahb_clk>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
uart2: serial@100800 {
pinctrl-0 = <&uart2_pins>;
pinctrl-names = "default";
compatible = "ns16550a";
reg = <0x100800 0x20>;
interrupts = <7>;
clocks = <&ahb_clk>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
reset@1070008 {
compatible = "mscc,serval-chip-reset";
reg = <0x1070008 0x4>;
};
gpio: pinctrl@1070034 {
compatible = "mscc,serval-pinctrl";
reg = <0x1070034 0x68>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&gpio 0 0 22>;
sgpio_pins: sgpio-pins {
pins = "GPIO_0", "GPIO_2", "GPIO_3", "GPIO_1";
function = "sio";
};
uart_pins: uart-pins {
pins = "GPIO_26", "GPIO_27";
function = "uart";
};
uart2_pins: uart2-pins {
pins = "GPIO_13", "GPIO_14";
function = "uart2";
};
};
spi0: spi-bitbang {
compatible = "mscc,luton-bb-spi";
status = "okay";
reg = <0x50 0x4>;
num-chipselects = <1>;
#address-cells = <1>;
#size-cells = <0>;
};
sgpio: gpio@10700b4 {
compatible = "mscc,luton-sgpio";
status = "disabled";
clocks = <&sys_clk>;
pinctrl-0 = <&sgpio_pins>;
pinctrl-names = "default";
reg = <0x10700b4 0x100>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&sgpio 0 0 64>;
};
};
};
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 Microsemi Corporation
*/
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mscc,servalt";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "mips,mips24KEc";
device_type = "cpu";
clocks = <&cpu_clk>;
reg = <0>;
};
};
aliases {
serial0 = &uart0;
};
cpuintc: interrupt-controller@0 {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
compatible = "mti,cpu-interrupt-controller";
};
cpu_clk: cpu-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <500000000>;
};
sys_clk: sys-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <250000000>;
};
ahb_clk: ahb-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <250000000>;
};
ahb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x70000000 0x2000000>;
interrupt-parent = <&intc>;
cpu_ctrl: syscon@0 {
compatible = "mscc,servalt-cpu-syscon", "syscon";
reg = <0x0 0x2c>;
};
intc: interrupt-controller@70 {
compatible = "mscc,servalt-icpu-intr";
reg = <0x70 0x74>;
#interrupt-cells = <1>;
interrupt-controller;
interrupt-parent = <&cpuintc>;
interrupts = <2>;
};
uart0: serial@100000 {
pinctrl-0 = <&uart_pins>;
pinctrl-names = "default";
compatible = "ns16550a";
reg = <0x100000 0x20>;
interrupts = <6>;
clocks = <&ahb_clk>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
uart2: serial@100800 {
pinctrl-0 = <&uart2_pins>;
pinctrl-names = "default";
compatible = "ns16550a";
reg = <0x100800 0x20>;
interrupts = <7>;
clocks = <&ahb_clk>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
reset@1010008 {
compatible = "mscc,servalt-chip-reset";
reg = <0x1010008 0x4>;
};
gpio: pinctrl@1010034 {
compatible = "mscc,servalt-pinctrl";
reg = <0x1010034 0x90>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&gpio 0 0 36>;
sgpio_pins: sgpio-pins {
pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
function = "sio";
};
uart_pins: uart-pins {
pins = "GPIO_6", "GPIO_7";
function = "uart";
};
uart2_pins: uart2-pins {
pins = "GPIO_20", "GPIO_21";
function = "uart2";
};
};
spi0: spi-bitbang {
compatible = "mscc,luton-bb-spi";
status = "okay";
reg = <0x50 0x4>;
num-chipselects = <1>;
#address-cells = <1>;
#size-cells = <0>;
};
sgpio: gpio@1010120 {
compatible = "mscc,ocelot-sgpio";
status = "disabled";
clocks = <&sys_clk>;
pinctrl-0 = <&sgpio_pins>;
pinctrl-names = "default";
reg = <0x1010120 0x100>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&sgpio 0 0 128>;
};
};
};
......@@ -35,3 +35,23 @@
status = "okay";
mscc,sgpio-ports = <0x00FFFFFF>;
};
&mdio0 {
status = "okay";
};
&port0 {
phy-handle = <&phy0>;
};
&port1 {
phy-handle = <&phy1>;
};
&port2 {
phy-handle = <&phy2>;
};
&port3 {
phy-handle = <&phy3>;
};
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 Microsemi Corporation
*/
/dts-v1/;
#include "mscc,serval.dtsi"
/ {
model = "Serval PCB105 Reference Board";
compatible = "mscc,serval-pcb105", "mscc,serval";
aliases {
spi0 = &spi0;
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
gpio-leds {
compatible = "gpio-leds";
status_green {
label = "pcb105:green:status";
gpios = <&sgpio 43 1>; /* p11.1 */
default-state = "on";
};
status_red {
label = "pcb105:red:status";
gpios = <&sgpio 11 1>; /* p11.0 */
default-state = "off";
};
};
};
&uart0 {
status = "okay";
};
&spi0 {
status = "okay";
spi-flash@0 {
compatible = "spi-flash";
spi-max-frequency = <18000000>; /* input clock */
reg = <0>; /* CS0 */
spi-cs-high;
};
};
&sgpio {
status = "okay";
sgpio-ports = <0x00FFFFFF>;
};
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 Microsemi Corporation
*/
/dts-v1/;
#include "mscc,serval.dtsi"
/ {
model = "Serval PCB106 Reference Board";
compatible = "mscc,serval-pcb106", "mscc,serval";
aliases {
spi0 = &spi0;
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
gpio-leds {
compatible = "gpio-leds";
status_green {
label = "pcb106:green:status";
gpios = <&sgpio 43 1>; /* p11.1 */
default-state = "on";
};
status_red {
label = "pcb106:red:status";
gpios = <&sgpio 11 1>; /* p11.0 */
default-state = "off";
};
};
};
&uart0 {
status = "okay";
};
&spi0 {
status = "okay";
spi-flash@0 {
compatible = "spi-flash";
spi-max-frequency = <18000000>; /* input clock */
reg = <0>; /* CS0 */
spi-cs-high;
};
};
&sgpio {
status = "okay";
sgpio-ports = <0x00FFFFFF>;
};
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 Microsemi Corporation
*/
/dts-v1/;
#include "mscc,servalt.dtsi"
/ {
model = "ServalT PCB116 Reference Board";
compatible = "mscc,servalt-pcb116", "mscc,servalt";
aliases {
spi0 = &spi0;
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
gpio-leds {
compatible = "gpio-leds";
status_green {
label = "pcb116:green:status";
gpios = <&sgpio 70 0>; /* p6.2 */
default-state = "on";
};
status_red {
label = "pcb116:red:status";
gpios = <&sgpio 102 0>; /* p6.3 */
default-state = "off";
};
};
};
&uart0 {
status = "okay";
};
&spi0 {
status = "okay";
spi-flash@0 {
compatible = "spi-flash";
spi-max-frequency = <18000000>; /* input clock */
reg = <0>; /* CS0 */
spi-cs-high;
};
};
&sgpio {
status = "okay";
sgpio-ports = <0x0000fe7f>;
};
......@@ -40,6 +40,20 @@ config SOC_JR2
help
This supports MSCC Jaguar2 family of SOCs.
config SOC_SERVALT
bool "Servalt SOC Family"
select SOC_VCOREIII
select MSCC_BB_SPI
help
This supports MSCC Servalt family of SOCs.
config SOC_SERVAL
bool "Serval SOC Family"
select SOC_VCOREIII
select MSCC_BB_SPI
help
This supports MSCC Serval family of SOCs.
endchoice
config SYS_CONFIG_NAME
......@@ -74,4 +88,7 @@ source "board/mscc/luton/Kconfig"
source "board/mscc/jr2/Kconfig"
source "board/mscc/servalt/Kconfig"
source "board/mscc/serval/Kconfig"
endmenu
......@@ -5,3 +5,4 @@ CFLAGS_cpu.o += -finline-limit=64000
obj-y += cpu.o dram.o reset.o phy.o lowlevel_init.o
obj-$(CONFIG_SOC_LUTON) += lowlevel_init_luton.o gpio.o
obj-$(CONFIG_SOC_OCELOT) += gpio.o
obj-$(CONFIG_SOC_SERVAL) += gpio.o
......@@ -87,11 +87,11 @@ int mach_cpu_init(void)
ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG);
#else
#ifdef CONFIG_SOC_OCELOT
#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_SERVAL)
writel(ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG);
#endif
#ifdef CONFIG_SOC_JR2
#if defined(CONFIG_SOC_JR2) || defined(CONFIG_SOC_SERVALT)
writel(ICPU_SPI_MST_CFG_FAST_READ_ENA +
ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
ICPU_SPI_MST_CFG_CLK_DIV(14), BASE_CFG + ICPU_SPI_MST_CFG);
......
......@@ -19,7 +19,8 @@ static inline int vcoreiii_train_bytelane(void)
ret = hal_vcoreiii_train_bytelane(0);
#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2)
#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
defined(CONFIG_SOC_SERVALT) || defined(CONFIG_SOC_SERVAL)
if (ret)
return ret;
ret = hal_vcoreiii_train_bytelane(1);
......
......@@ -21,6 +21,16 @@
#include <mach/jr2/jr2_devcpu_gcb.h>
#include <mach/jr2/jr2_devcpu_gcb_miim_regs.h>
#include <mach/jr2/jr2_icpu_cfg.h>
#elif defined(CONFIG_SOC_SERVALT)
#include <mach/servalt/servalt.h>
#include <mach/servalt/servalt_devcpu_gcb.h>
#include <mach/servalt/servalt_devcpu_gcb_miim_regs.h>
#include <mach/servalt/servalt_icpu_cfg.h>
#elif defined(CONFIG_SOC_SERVAL)
#include <mach/serval/serval.h>
#include <mach/serval/serval_devcpu_gcb.h>
#include <mach/serval/serval_devcpu_gcb_miim_regs.h>
#include <mach/serval/serval_icpu_cfg.h>
#else
#error Unsupported platform</