Commit d1c3d8bd authored by Daniel Schwierzeck's avatar Daniel Schwierzeck

MIPS: start.S: make boot config at offset 0x10 configurable

Some MIPS systems store some board-specific boot configuration
in the U-Boot binary at offset 0x10. This is used by Malta boards
and by Lantiq/Intel SoC's when booting from parallel NOR flash.

Convert the hard-coded values to Kconfig options to remove such
board-specific stuff out of the generic start.S code. This also
deprecates the config option CONFIG_SYS_XWAY_EBU_BOOTCFG.
Signed-off-by: Daniel Schwierzeck's avatarDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
parent 32f3179a
......@@ -542,11 +542,6 @@ The following options need to be configured:
CONF_CM_CACHABLE_CUW
CONF_CM_CACHABLE_ACCELERATED
CONFIG_SYS_XWAY_EBU_BOOTCFG
Special option for Lantiq XWAY SoCs for booting from NOR flash.
See also arch/mips/cpu/mips32/start.S.
CONFIG_XWAY_SWAP_BYTES
Enable compilation of tools/xway-swap-bytes needed for Lantiq
......
......@@ -28,6 +28,7 @@ config TARGET_MALTA
select DM_SERIAL
select DYNAMIC_IO_PORT_BASE
select MIPS_CM
select MIPS_INSERT_BOOT_CONFIG
select MIPS_L1_CACHE_SHIFT_6
select MIPS_L2_CACHE
select OF_CONTROL
......@@ -390,6 +391,28 @@ config MIPS_CM
wish U-Boot to configure it or make use of it to retrieve system
information such as cache configuration.
config MIPS_INSERT_BOOT_CONFIG
bool
default n
help
Enable this to insert some board-specific boot configuration in
the U-Boot binary at offset 0x10.
config MIPS_BOOT_CONFIG_WORD0
hex
depends on MIPS_INSERT_BOOT_CONFIG
default 0x420 if TARGET_MALTA
default 0x0
help
Value which is inserted as boot config word 0.
config MIPS_BOOT_CONFIG_WORD1
hex
depends on MIPS_INSERT_BOOT_CONFIG
default 0x0
help
Value which is inserted as boot config word 1.
endif
endmenu
......@@ -84,25 +84,14 @@ ENTRY(_start)
b reset
mtc0 zero, CP0_COUNT # clear cp0 count for most accurate boot timing
#if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG)
#if defined(CONFIG_MIPS_INSERT_BOOT_CONFIG)
/*
* Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
* access external NOR flashes. If the board boots from NOR flash the
* internal BootROM does a blind read at address 0xB0000010 to read the
* initial configuration for that EBU in order to access the flash
* device with correct parameters. This config option is board-specific.
* Store some board-specific boot configuration. This is used by some
* MIPS systems like Malta.
*/
.org 0x10
.word CONFIG_SYS_XWAY_EBU_BOOTCFG
.word 0x0
#endif
#if defined(CONFIG_MALTA)
/*
* Linux expects the Board ID here.
*/
.org 0x10
.word 0x00000420 # 0x420 (Malta Board with CoreLV)
.word 0x00000000
.word CONFIG_MIPS_BOOT_CONFIG_WORD0
.word CONFIG_MIPS_BOOT_CONFIG_WORD1
#endif
#if defined(CONFIG_ROM_EXCEPTION_VECTORS)
......
......@@ -4421,7 +4421,6 @@ CONFIG_SYS_XHCI_USB1_ADDR
CONFIG_SYS_XHCI_USB2_ADDR
CONFIG_SYS_XHCI_USB3_ADDR
CONFIG_SYS_XIMG_LEN
CONFIG_SYS_XWAY_EBU_BOOTCFG
CONFIG_SYS_ZYNQ_QSPI_WAIT
CONFIG_SYS_ZYNQ_SPI_WAIT
CONFIG_SYS_i2C_FSL
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment