1. 15 Oct, 2012 1 commit
  2. 03 Oct, 2012 3 commits
  3. 02 Oct, 2012 3 commits
  4. 29 Sep, 2012 1 commit
  5. 27 Sep, 2012 3 commits
  6. 02 Sep, 2012 3 commits
  7. 01 Sep, 2012 1 commit
  8. 23 Aug, 2012 2 commits
    • Scott Wood's avatar
      powerpc/fsl-corenet: work around erratum A004510 · 33eee330
      Scott Wood authored
      Erratum A004510 says that under certain load conditions, modified
      cache lines can be discarded, causing data corruption.
      
      To work around this, several CCSR and DCSR register updates need to be
      made in a careful manner, so that there is no other transaction in
      corenet when the update is made.
      
      The update is made from a locked cacheline, with a delay before to flush
      any previous activity, and a delay after to flush the CCSR/DCSR update.
      We can't use a readback because that would be another corenet
      transaction, which is not allowed.
      
      We lock the subsequent cacheline to prevent it from being fetched while
      we're executing the previous cacheline.  It is filled with nops so that a
      branch doesn't cause us to fetch another cacheline.
      
      Ordinarily we are running in a cache-inhibited mapping at this point, so
      we temporarily change that.  We make it guarded so that we should never
      see a speculative load, and we never do an explicit load.  Thus, only the
      I-cache should ever fill from this mapping, and we flush/unlock it
      afterward.  Thus we should avoid problems from any potential cache
      aliasing between inhibited and non-inhibited mappings.
      
      NOTE that if PAMU is used with this patch, it will need to use a
      dedicated LAW as described in the erratum.  This is the responsibility
      of the OS that sets up PAMU.
      Signed-off-by: Scott Wood's avatarScott Wood <scottwood@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      33eee330
    • Liu Gang's avatar
      powerpc/corenet_ds: Update README and README.srio-pcie-boot-corenet · fc54c7fa
      Liu Gang authored
      Added descriptions about boot from PCIE in the files README and
      doc/README.srio-pcie-boot-corenet, and changed the name of the
      doc/README.srio-boot-corenet to doc/README.srio-pcie-boot-corenet.
      Signed-off-by: default avatarLiu Gang <Gang.Liu@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      fc54c7fa
  9. 12 Jul, 2012 1 commit
  10. 09 Jul, 2012 1 commit
  11. 06 Jul, 2012 1 commit
  12. 23 May, 2012 2 commits
  13. 15 May, 2012 1 commit
  14. 25 Apr, 2012 2 commits
    • Liu Gang's avatar
      powerpc/corenet_ds: Slave reads ENV from master when boot from SRIO · 0a85a9e7
      Liu Gang authored
      When boot from SRIO, slave's ENV can be stored in master's memory space,
      then slave can fetch the ENV through SRIO interface.
      
      NOTE: Because the slave can not erase, write master's NOR flash by SRIO
      	  interface, so it can not modify the ENV parameters stored in
      	  master's NOR flash using "saveenv" or other commands.
      
      Master needs to:
      	1. Put the slave's ENV into it's own memory space.
      	2. Set an inbound SRIO window covered slave's ENV stored in master's
      	   memory space.
      Slave needs to:
      	1. Set a specific TLB entry in order to fetch ucode and ENV from master.
      	2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode and ENV.
      Signed-off-by: default avatarLiu Gang <Gang.Liu@freescale.com>
      Signed-off-by: default avatarShaohui Xie <Shaohui.Xie@freescale.com>
      0a85a9e7
    • Liu Gang's avatar
      powerpc/corenet_ds: Slave module for boot from SRIO · 292dc6c5
      Liu Gang authored
      For the powerpc processors with SRIO interface, boot location can be configured
      from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash
      for u-boot image. The image can be fetched from another processor's memory
      space by SRIO link connected between them.
      
      The processor boots from SRIO is slave, the processor boots from normal flash
      memory space and can help slave to boot from its memory space is master.
      They are different environments and requirements:
      
      master:
      	1. NOR flash for its own u-boot image, ucode and ENV space.
      	2. Slave's u-boot image in master NOR flash.
      	3. Normally boot from local NOR flash.
      	4. Configure SRIO switch system if needed.
      slave:
      	1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
      	2. Boot location should be set to SRIO1 or SRIO2 by RCW.
      	3. RCW should configure the SerDes, SRIO interfaces correctly.
      	4. Slave must be powered on after master's boot.
      	5. Must define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE because of no ucode
      	   locally.
      
      For the slave module, need to finish these processes:
      	1. Set the boot location to SRIO1 or SRIO2 by RCW.
          2. Set a specific TLB entry for the boot process.
      	3. Set a LAW entry with the TargetID SRIO1 or SRIO2 for the boot.
      	4. Slave's u-boot image should be generated specifically by
      	   make xxxx_SRIOBOOT_SLAVE_config.
      	   This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.
      Signed-off-by: default avatarLiu Gang <Gang.Liu@freescale.com>
      Signed-off-by: default avatarShaohui Xie <Shaohui.Xie@freescale.com>
      292dc6c5
  15. 19 Apr, 2012 1 commit
  16. 11 Apr, 2012 1 commit
  17. 02 Apr, 2012 1 commit
    • Daniel Schwierzeck's avatar
      MIPS: fix endianess handling · 6cb461b4
      Daniel Schwierzeck authored
      Make endianess of target CPU configurable. Use the new config
      option for dbau1550_el and pb1000 boards.
      
      Adapt linking of standalone applications to pass through
      endianess options to LD.
      
      Build tested with:
       - ELDK 4 mips_4KC- and mips4KCle
       - Sourcery CodeBench Lite 2011.03-93
      
      With this patch all 26 MIPS boards can be compiled now in one step by
      running "MAKEALL -a mips".
      Signed-off-by: Daniel Schwierzeck's avatarDaniel Schwierzeck <daniel.schwierzeck@googlemail.com>
      6cb461b4
  18. 30 Mar, 2012 2 commits
    • Marek Vasut's avatar
      BOOT: Add RAW ramdisk support to bootz · 017e1f3f
      Marek Vasut authored
      This patch allows loading RAW ramdisk via bootz command. The raw ramdisk is
      loaded only in case it's size is specified:
      
        bootz <kernel addr> <ramdisk addr>:<ramdisk size> <fdt addr>
      
      For example:
      
        bootz 0x42000000 0x43000000:0x12345 0x44000000
      Signed-off-by: Marek Vasut's avatarMarek Vasut <marex@denx.de>
      Signed-off-by: default avatarRob Herring <rob.herring@calxeda.com>
      Cc: Tom Warren <TWarren@nvidia.com>
      Cc: albert.u.boot@aribaud.net
      Cc: afleming@gmail.com
      Cc: Simon Glass <sjg@chromium.org>
      Cc: Stephen Warren <swarren@nvidia.com>
      Cc: Nicolas Pitre <nico@fluxnic.net>
      Cc: Wolfgang Denk <wd@denx.de>
      Cc: Detlev Zundel <dzu@denx.de>
      017e1f3f
    • Marek Vasut's avatar
      BOOT: Add "bootz" command to boot Linux zImage on ARM · 44f074c7
      Marek Vasut authored
      This command boots Linux zImage from where the zImage is loaded to. Passing
      initrd and fdt is supported.
      
      Tested on i.MX28 based DENX M28EVK
      Tested on PXA270 based Voipac PXA270.
      
      NOTE: This currently only supports ARM, but other architectures can be easily
      added by defining bootz_setup().
      Signed-off-by: default avatarMarek Vasut <marek.vasut@gmail.com>
      Cc: Tom Warren <TWarren@nvidia.com>
      Cc: albert.u.boot@aribaud.net
      Cc: afleming@gmail.com,
      Cc: Simon Glass <sjg@chromium.org>,
      Cc: Stephen Warren <swarren@nvidia.com>
      Cc: Nicolas Pitre <nico@fluxnic.net>
      Cc: Wolfgang Denk <wd@denx.de>
      Cc: Detlev Zundel <dzu@denx.de>
      44f074c7
  19. 29 Mar, 2012 1 commit
  20. 28 Mar, 2012 1 commit
    • Vipin KUMAR's avatar
      Enable high speed support for USB device framework and usbtty · f9da0f89
      Vipin KUMAR authored
      This patch adds the support for high speed in usb device framework and usbtty
      driver. This feature has been kept within a macro CONFIG_USBD_HS, so the board
      configuration files have to define this macro to enable high speed support.
      
      Along with that specific peripheral drivers also need to define a function to
      let the framework know that the enumeration has happened at high speed.
      This function prototype is "int is_usbd_high_speed(void)"
      Signed-off-by: default avatarVipin Kumar <vipin.kumar@st.com>
      Signed-off-by: default avatarAmit Virdi <amit.virdi@st.com>
      f9da0f89
  21. 26 Mar, 2012 2 commits
  22. 23 Mar, 2012 1 commit
  23. 18 Mar, 2012 1 commit
    • Simon Glass's avatar
      bootstage: Implement core microsecond boot time measurement · 3a608ca0
      Simon Glass authored
      This defines the basics of a new boot time measurement feature. This allows
      logging of very accurate time measurements as the boot proceeds, by using
      an available microsecond counter.
      
      To enable the feature, define CONFIG_BOOTSTAGE in your board config file.
      Also available is CONFIG_BOOTSTAGE_REPORT which will cause a report to be
      printed just before handing off to the OS.
      
      Most IDs are not named at this stage. For that I would first like to
      renumber them all.
      
      Timer summary in microseconds:
             Mark    Elapsed  Stage
                0          0  reset
          205,000    205,000  board_init_f
        6,053,000  5,848,000  bootm_start
        6,053,000          0  id=1
        6,058,000      5,000  id=101
        6,058,000          0  id=100
        6,061,000      3,000  id=103
        6,064,000      3,000  id=104
        6,093,000     29,000  id=107
        6,093,000          0  id=106
        6,093,000          0  id=105
        6,093,000          0  id=108
        7,089,000    996,000  id=7
        7,089,000          0  id=15
        7,089,000          0  id=8
        7,097,000      8,000  start_kernel
      Signed-off-by: Simon Glass's avatarSimon Glass <sjg@chromium.org>
      3a608ca0
  24. 27 Feb, 2012 1 commit
    • Shawn Guo's avatar
      common/image.c: align usage of fdt_high with initrd_high · fa34f6b2
      Shawn Guo authored
      The commit message of a28afca5 (Add uboot "fdt_high" enviroment variable)
      states that fdt_high behaves similarly to the existing initrd_high.
      But fdt_high actually has an outstanding difference from initrd_high.
      The former specifies the start address, while the later specifies the
      end address.
      
      As fdt_high and initrd_high will likely be used together, it'd be nice
      to have them behave same.  The patch changes the behavior of fdt_high
      to have it aligned with initrd_high.
      
      The document of fdt_high in README is updated with an example to
      demonstrate the usage of this environment variable.
      Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
      Acked-by: Simon Glass's avatarSimon Glass <sjg@chromium.org>
      fa34f6b2
  25. 12 Feb, 2012 2 commits
  26. 19 Jan, 2012 1 commit