Commit dc470834 authored by Eugen Hristev's avatar Eugen Hristev

clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics

This SoC has the 5th divisor for the mck0 master clock.
Adapt the characteristics accordingly.
Reported-by: default avatarMihai Sain <mihai.sain@microchip.com>
Signed-off-by: Eugen Hristev's avatarEugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: default avatarClaudiu Beznea <claudiu.beznea@microchip.com>
parent dff39042
......@@ -189,13 +189,13 @@ static const struct clk_pll_layout pll_layout_divio = {
/* MCK0 characteristics. */
static const struct clk_master_characteristics mck0_characteristics = {
.output = { .min = 140000000, .max = 200000000 },
.divisors = { 1, 2, 4, 3 },
.divisors = { 1, 2, 4, 3, 5 },
.have_div3_pres = 1,
};
/* MCK0 layout. */
static const struct clk_master_layout mck0_layout = {
.mask = 0x373,
.mask = 0x773,
.pres_shift = 4,
.offset = 0x28,
};
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment