Commit 41eee945 authored by David Wu's avatar David Wu Committed by Kever Yang

pinctrl: rockchip: Add pinctrl support for rk3308

An iomux register contains 8 pins, each of which is represented
by 2 bits, but the register offset is 0x8.

For example, GRF_GPIO0A_IOMUX offset is 0x0, but GRF_GPIO0B_IOMUX
offset is 0x8, the offset 0x4 is reserved.

So add a type IOMUX_8WIDTH_2BIT to calculate offset.
Signed-off-by: default avatarDavid Wu <david.wu@rock-chips.com>
Reviewed-by: Kever Yang's avatarKever Yang <kever.yang@rock-chips.com>
parent e0e6c96a
......@@ -9,6 +9,7 @@ obj-$(CONFIG_ROCKCHIP_RK3128) += pinctrl-rk3128.o
obj-$(CONFIG_ROCKCHIP_RK3188) += pinctrl-rk3188.o
obj-$(CONFIG_ROCKCHIP_RK322X) += pinctrl-rk322x.o
obj-$(CONFIG_ROCKCHIP_RK3288) += pinctrl-rk3288.o
obj-$(CONFIG_ROCKCHIP_RK3308) += pinctrl-rk3308.o
obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o
obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o
obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o
......
This diff is collapsed.
......@@ -539,7 +539,8 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *d
* 4bit iomux'es are spread over two registers.
*/
inc = (iom->type & (IOMUX_WIDTH_4BIT |
IOMUX_WIDTH_3BIT)) ? 8 : 4;
IOMUX_WIDTH_3BIT |
IOMUX_8WIDTH_2BIT)) ? 8 : 4;
if (iom->type & IOMUX_SOURCE_PMU)
pmu_offs += inc;
else
......
......@@ -16,6 +16,7 @@
#define IOMUX_SOURCE_PMU BIT(2)
#define IOMUX_UNROUTED BIT(3)
#define IOMUX_WIDTH_3BIT BIT(4)
#define IOMUX_8WIDTH_2BIT BIT(5)
/**
* Defined some common pins constants
......
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