Commit 88718be3 authored by Miquel Raynal's avatar Miquel Raynal Committed by Tom Rini

mtd: rename CONFIG_NAND -> CONFIG_MTD_RAW_NAND

Add more clarity by changing the Kconfig entry name.
Signed-off-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
[trini: Re-run migration, update a few more cases]
Signed-off-by: Tom Rini's avatarTom Rini <trini@konsulko.com>
Reviewed-by: default avatarBoris Brezillon <boris.brezillon@bootlin.com>
parent 94d022bb
......@@ -974,7 +974,7 @@ config ARCH_SUNXI
select SPL_USE_TINY_PRINTF
imply CMD_DM
imply CMD_GPT
imply CMD_UBI if NAND
imply CMD_UBI if MTD_RAW_NAND
imply DISTRO_DEFAULTS
imply FAT_WRITE
imply FIT
......@@ -1004,7 +1004,7 @@ config ARCH_VF610
select CPU_V7A
select SYS_FSL_ERRATUM_ESDHC111
imply CMD_MTDPARTS
imply NAND
imply MTD_RAW_NAND
config ARCH_ZYNQ
bool "Xilinx Zynq based platform"
......
......@@ -80,7 +80,7 @@ config CMD_HDMIDETECT
config CMD_NANDBCB
bool "i.MX6 NAND Boot Control Block(BCB) command"
depends on NAND && CMD_MTDPARTS
depends on MTD_RAW_NAND && CMD_MTDPARTS
select BCH if MX6UL || MX6ULL
default y if (ARCH_MX6 && NAND_MXS) || (ARCH_MX7 && NAND_MXS)
help
......
......@@ -25,7 +25,7 @@ const struct gpmc *gpmc_cfg = (struct gpmc *)GPMC_BASE;
#if defined(CONFIG_NOR)
char gpmc_cs0_flash = MTD_DEV_TYPE_NOR;
#elif defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND)
#elif defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_CMD_NAND)
char gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
#elif defined(CONFIG_CMD_ONENAND)
char gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
......@@ -93,7 +93,7 @@ void set_gpmc_cs0(int flash_type)
STNOR_GPMC_CONFIG7
};
#endif
#if defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND)
#if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_CMD_NAND)
const u32 gpmc_regs_nand[GPMC_MAX_REG] = {
M_NAND_GPMC_CONFIG1,
M_NAND_GPMC_CONFIG2,
......@@ -128,7 +128,7 @@ void set_gpmc_cs0(int flash_type)
GPMC_SIZE_16M)));
break;
#endif
#if defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND)
#if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_CMD_NAND)
case MTD_DEV_TYPE_NAND:
gpmc_regs = gpmc_regs_nand;
base = CONFIG_SYS_NAND_BASE;
......
......@@ -150,7 +150,7 @@ int board_init(void)
hw_watchdog_init();
#endif
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_NAND
#ifdef CONFIG_MTD_RAW_NAND
gpmc_init();
#endif
return 0;
......
......@@ -118,7 +118,7 @@ static struct module_pin_mux mii2_pin_mux[] = {
{OFFSET(gpmc_be1n), (MODE(1) | RXACTIVE)},/* MII1_COL */
{-1},
};
#ifdef CONFIG_NAND
#ifdef CONFIG_MTD_RAW_NAND
static struct module_pin_mux nand_pin_mux[] = {
{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
......@@ -180,7 +180,7 @@ static struct module_pin_mux gpIOs[] = {
{OFFSET(mcasp0_axr0), (MODE(7) | PULLUDDIS) },
/* GPIO3_17 (MCASP0_AHCLKR) - ETH2_LEDY */
{OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS) },
#ifndef CONFIG_NAND
#ifndef CONFIG_MTD_RAW_NAND
/* GPIO2_3 - NAND_OE */
{OFFSET(gpmc_oen_ren), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
/* GPIO2_4 - NAND_WEN */
......@@ -241,7 +241,7 @@ void enable_board_pin_mux(void)
configure_module_pin_mux(i2c0_pin_mux);
configure_module_pin_mux(mii1_pin_mux);
configure_module_pin_mux(mii2_pin_mux);
#ifdef CONFIG_NAND
#ifdef CONFIG_MTD_RAW_NAND
configure_module_pin_mux(nand_pin_mux);
#elif defined(CONFIG_MMC)
configure_module_pin_mux(mmc1_pin_mux);
......
......@@ -292,7 +292,7 @@ int board_init(void)
#endif
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
#if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
gpmc_init();
#endif
return 0;
......
......@@ -180,7 +180,7 @@ int board_init(void)
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_NAND
#ifdef CONFIG_MTD_RAW_NAND
gpmc_init();
#endif
return 0;
......
......@@ -39,7 +39,7 @@ static struct module_pin_mux guardian_interfaces_pin_mux[] = {
{-1},
};
#ifdef CONFIG_NAND
#ifdef CONFIG_MTD_RAW_NAND
static struct module_pin_mux nand_pin_mux[] = {
{OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)},
{OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)},
......@@ -82,7 +82,7 @@ void enable_i2c0_pin_mux(void)
void enable_board_pin_mux(void)
{
#ifdef CONFIG_NAND
#ifdef CONFIG_MTD_RAW_NAND
configure_module_pin_mux(nand_pin_mux);
#endif
configure_module_pin_mux(guardian_interfaces_pin_mux);
......
......@@ -444,7 +444,7 @@ int board_init(void)
puts("EEPROM Content Invalid.\n");
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
#if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
gpmc_init();
#endif
shc_request_gpio();
......
......@@ -221,7 +221,7 @@ int board_init(void)
else
config_board_mux(MUX_TYPE_SDHC);
#if defined(CONFIG_NAND) && defined(CONFIG_FSL_QSPI)
#if defined(CONFIG_MTD_RAW_NAND) && defined(CONFIG_FSL_QSPI)
val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
......
......@@ -76,7 +76,7 @@ int checkboard(void)
printf("NOR vBank%d\n", reg);
}
#elif defined(CONFIG_TARGET_T1023RDB)
#ifdef CONFIG_NAND
#ifdef CONFIG_MTD_RAW_NAND
puts("NAND\n");
#else
printf("NOR vBank%d\n", t1023rdb_ctrl(I2C_GET_BANK));
......
......@@ -42,7 +42,7 @@ static void ci20_mux_eth(void)
{
void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
#ifdef CONFIG_NAND
#ifdef CONFIG_MTD_RAW_NAND
/* setup pins (some already setup for NAND) */
writel(0x04030000, gpio_regs + GPIO_PXINTC(0));
writel(0x04030000, gpio_regs + GPIO_PXMASKC(0));
......
......@@ -82,7 +82,7 @@ static struct module_pin_mux cbmux_pin_mux[] = {
{-1},
};
#ifdef CONFIG_NAND
#ifdef CONFIG_MTD_RAW_NAND
static struct module_pin_mux nand_pin_mux[] = {
{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
......@@ -118,7 +118,7 @@ void enable_board_pin_mux()
configure_module_pin_mux(rmii1_pin_mux);
configure_module_pin_mux(mmc0_pin_mux);
configure_module_pin_mux(cbmux_pin_mux);
#ifdef CONFIG_NAND
#ifdef CONFIG_MTD_RAW_NAND
configure_module_pin_mux(nand_pin_mux);
#endif
#ifdef CONFIG_SPI
......
......@@ -72,7 +72,7 @@ static struct module_pin_mux cbmux_pin_mux[] = {
{-1},
};
#ifdef CONFIG_NAND
#ifdef CONFIG_MTD_RAW_NAND
static struct module_pin_mux nand_pin_mux[] = {
{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
......@@ -108,7 +108,7 @@ void enable_board_pin_mux(void)
configure_module_pin_mux(rmii1_pin_mux);
configure_module_pin_mux(mmc0_pin_mux);
configure_module_pin_mux(cbmux_pin_mux);
#ifdef CONFIG_NAND
#ifdef CONFIG_MTD_RAW_NAND
configure_module_pin_mux(nand_pin_mux);
#endif
#ifdef CONFIG_SPI
......
......@@ -26,7 +26,7 @@ static struct module_pin_mux uart0_pin_mux[] = {
{-1},
};
#ifdef CONFIG_NAND
#ifdef CONFIG_MTD_RAW_NAND
static struct module_pin_mux nand_pin_mux[] = {
{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
......@@ -169,7 +169,7 @@ void enable_board_pin_mux(void)
{
configure_module_pin_mux(uart0_pin_mux);
configure_module_pin_mux(i2c1_pin_mux);
#ifdef CONFIG_NAND
#ifdef CONFIG_MTD_RAW_NAND
configure_module_pin_mux(nand_pin_mux);
#endif
#ifndef CONFIG_NO_ETH
......
......@@ -21,7 +21,7 @@ In order to accomodate that, we create a tool that will generate an
SPL image that is ready to be programmed directly embedding the ECCs,
randomized, and with the necessary bits needed to reduce the number of
bitflips. The U-Boot build system, when configured for the NAND (with
CONFIG_NAND=y) will also generate the image sunxi-spl-with-ecc.bin
CONFIG_MTD_RAW_NAND=y) will also generate the image sunxi-spl-with-ecc.bin
that will have been generated by that tool.
In order to flash your U-Boot image onto a board, assuming that the
......
......@@ -710,7 +710,7 @@ int board_init(void)
#endif
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
#if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
gpmc_init();
#endif
......
......@@ -195,7 +195,7 @@ static struct module_pin_mux rmii1_pin_mux[] = {
{-1},
};
#ifdef CONFIG_NAND
#ifdef CONFIG_MTD_RAW_NAND
static struct module_pin_mux nand_pin_mux[] = {
{OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */
{OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */
......@@ -360,7 +360,7 @@ void enable_board_pin_mux(void)
/* Beaglebone pinmux */
configure_module_pin_mux(mii1_pin_mux);
configure_module_pin_mux(mmc0_pin_mux);
#if defined(CONFIG_NAND)
#if defined(CONFIG_MTD_RAW_NAND)
configure_module_pin_mux(nand_pin_mux);
#elif defined(CONFIG_NOR)
configure_module_pin_mux(bone_norcape_pin_mux);
......@@ -376,7 +376,7 @@ void enable_board_pin_mux(void)
if (profile & ~PROFILE_2)
configure_module_pin_mux(i2c1_pin_mux);
/* Profiles 2 & 3 don't have NAND */
#ifdef CONFIG_NAND
#ifdef CONFIG_MTD_RAW_NAND
if (profile & ~(PROFILE_2 | PROFILE_3))
configure_module_pin_mux(nand_pin_mux);
#endif
......@@ -404,7 +404,7 @@ void enable_board_pin_mux(void)
}
/* Beaglebone LT pinmux */
configure_module_pin_mux(mmc0_pin_mux);
#if defined(CONFIG_NAND) && defined(CONFIG_EMMC_BOOT)
#if defined(CONFIG_MTD_RAW_NAND) && defined(CONFIG_EMMC_BOOT)
configure_module_pin_mux(nand_pin_mux);
#elif defined(CONFIG_NOR) && defined(CONFIG_EMMC_BOOT)
configure_module_pin_mux(bone_norcape_pin_mux);
......
......@@ -73,7 +73,7 @@ static struct module_pin_mux gpio5_7_pin_mux[] = {
{-1},
};
#ifdef CONFIG_NAND
#ifdef CONFIG_MTD_RAW_NAND
static struct module_pin_mux nand_pin_mux[] = {
{OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */
{OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */
......@@ -128,18 +128,18 @@ void enable_board_pin_mux(void)
if (board_is_evm()) {
configure_module_pin_mux(gpio5_7_pin_mux);
configure_module_pin_mux(rgmii1_pin_mux);
#if defined(CONFIG_NAND)
#if defined(CONFIG_MTD_RAW_NAND)
configure_module_pin_mux(nand_pin_mux);
#endif
} else if (board_is_sk() || board_is_idk()) {
configure_module_pin_mux(rgmii1_pin_mux);
#if defined(CONFIG_NAND)
#if defined(CONFIG_MTD_RAW_NAND)
printf("Error: NAND flash not present on this board\n");
#endif
configure_module_pin_mux(qspi_pin_mux);
} else if (board_is_eposevm()) {
configure_module_pin_mux(rmii1_pin_mux);
#if defined(CONFIG_NAND)
#if defined(CONFIG_MTD_RAW_NAND)
configure_module_pin_mux(nand_pin_mux);
#else
configure_module_pin_mux(qspi_pin_mux);
......
......@@ -784,7 +784,7 @@ void set_muxconf_regs(void)
early_padconf, ARRAY_SIZE(early_padconf));
}
#if defined(CONFIG_NAND)
#if defined(CONFIG_MTD_RAW_NAND)
static int nand_sw_detect(void)
{
int rc;
......
......@@ -25,7 +25,7 @@ DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
#if defined(CONFIG_NAND)
#if defined(CONFIG_MTD_RAW_NAND)
gpmc_init();
#endif
return 0;
......
......@@ -265,7 +265,7 @@ int board_init(void)
#endif
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
#if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
gpmc_init();
#endif
return 0;
......
......@@ -112,7 +112,7 @@ void enable_board_pin_mux()
configure_module_pin_mux(rmii1_pin_mux);
configure_module_pin_mux(mmc0_pin_mux);
#if defined(CONFIG_NAND)
#if defined(CONFIG_MTD_RAW_NAND)
configure_module_pin_mux(nand_pin_mux);
#endif
}
......@@ -1954,7 +1954,7 @@ config CMD_JFFS2
config CMD_MTDPARTS
bool "MTD partition support"
select MTD_DEVICE if (CMD_NAND || NAND)
select MTD_DEVICE if (CMD_NAND || MTD_RAW_NAND)
help
MTD partitioning tool support.
It is strongly encouraged to avoid using this command
......
......@@ -303,7 +303,7 @@ config NOR_BOOT
config NAND_BOOT
bool "Support for booting from NAND flash"
default n
imply NAND
imply MTD_RAW_NAND
help
Enabling this will make a U-Boot binary that is capable of being
booted via NAND flash. This is not a must, some SoCs need this,
......@@ -312,7 +312,7 @@ config NAND_BOOT
config ONENAND_BOOT
bool "Support for booting from ONENAND"
default n
imply NAND
imply MTD_RAW_NAND
help
Enabling this will make a U-Boot binary that is capable of being
booted via ONENAND. This is not a must, some SoCs need this,
......
......@@ -46,7 +46,7 @@ CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
......
......@@ -46,7 +46,7 @@ CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
......
......@@ -37,7 +37,7 @@ CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_FSL_CAAM=y
# CONFIG_MMC is not set
CONFIG_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
......
......@@ -36,7 +36,7 @@ CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_FSL_CAAM=y
# CONFIG_MMC is not set
CONFIG_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
......
......@@ -44,7 +44,7 @@ CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
......
......@@ -44,7 +44,7 @@ CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
......
......@@ -44,7 +44,7 @@ CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
......
......@@ -17,7 +17,7 @@ CONFIG_ENV_UBI_PART="UBI"
CONFIG_ENV_UBI_VOLUME="uboot-env"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_MMC is not set
CONFIG_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
CONFIG_SYS_NAND_PAGE_SIZE=0x1000
CONFIG_SYS_NAND_OOBSIZE=0x100
......
......@@ -161,7 +161,7 @@ CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_PHY_MARVELL=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
......
......@@ -160,7 +160,7 @@ CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_PHY_MARVELL=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
......
......@@ -17,7 +17,7 @@ CONFIG_CMD_MTDPARTS=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-r16-nintendo-nes-classic-edition"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_MMC is not set
CONFIG_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
......
......@@ -52,7 +52,7 @@ CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
......
......@@ -51,7 +51,7 @@ CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
......
......@@ -52,7 +52,7 @@ CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
......
......@@ -51,7 +51,7 @@ CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
......
......@@ -54,7 +54,7 @@ CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_NAND=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
......