Commit ce28d7ac authored by Masahiro Yamada's avatar Masahiro Yamada Committed by Tom Rini

Makefile: prepare for using Kbuild-style Makefile

Every makefile in sub directories has common lines
at the top and the bottom.
This commit pushes the common parts into script/Makefile.build.

Going forward sub-makefiles only need to describe this part:

    COBJS := ...
    COBJS += ...
    SOBJS := ...

But using obj-y is preferable to prepare for switching to Kbuild.

The conventional (non-Kbuild) Makefile style is still supported.
This is achieved by greping the Makefile before entering into it.
U-Boot conventional sub makefiles always include some other makefiles.
So the build system searches a line beginning with "include" keyword
in the makefile in order to distinguish which style it is.
If the Makefile include a "include" line, we assume it is a conventional
U-Boot style. Otherwise, it is treated as a Kbuild-style makefile.

With this tweak, we can switch sub-makefiles
from U-Boot style to Kbuild style little by little.

obj-y := foo/
syntax (descending into the sub directory) is not supportd yet.
It will be implemented in the upcomming commit.
Signed-off-by: default avatarMasahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@ti.com>
parent 9d33fb4a
......@@ -595,14 +595,32 @@ ifeq ($(CONFIG_KALLSYMS),y)
$(GEN_UBOOT) $(obj)common/system_map.o
endif
# Tentative step for Kbuild-style makefiles coexist with conventional U-Boot style makefiles
# U-Boot conventional sub makefiles always include some other makefiles.
# So, the build system searches a line beginning with "include" before entering into the sub makefile
# in order to distinguish which style it is.
# If the Makefile include a "include" line, we assume it is an U-Boot style makefile.
# Otherwise, it is treated as a Kbuild-style makefile.
select_makefile = \
+if grep -q "^include" $1/Makefile; then \
$(MAKE) -C $1; \
else \
$(MAKE) -C $1 -f $(TOPDIR)/scripts/Makefile.build; \
mv $(dir $@)built-in.o $@; \
fi
# We do not need to build $(OBJS) explicitly.
# It is built while we are at $(CPUDIR)/lib$(CPU).o build.
$(OBJS): depend
$(MAKE) -C $(CPUDIR) $(if $(REMOTE_BUILD),$@,$(notdir $@))
if grep -q "^include" $(CPUDIR)/Makefile; then \
$(MAKE) -C $(CPUDIR) $(if $(REMOTE_BUILD),$@,$(notdir $@)); \
fi
$(LIBS): depend $(SUBDIR_TOOLS)
$(MAKE) -C $(dir $(subst $(obj),,$@))
+$(call select_makefile, $(dir $(subst $(obj),,$@)))
$(LIBBOARD): depend $(LIBS)
$(MAKE) -C $(dir $(subst $(obj),,$@))
+$(call select_makefile, $(dir $(subst $(obj),,$@)))
$(SUBDIRS): depend
$(MAKE) -C $@ all
......@@ -630,6 +648,13 @@ $(obj)tpl/u-boot-tpl.bin: $(SUBDIR_TOOLS) depend
updater:
$(MAKE) -C tools/updater all
select_makefile2 = \
if grep -q "^include" $1/Makefile; then \
$(MAKE) -C $1 _depend; \
else \
$(MAKE) -C $1 -f $(TOPDIR)/scripts/Makefile.build _depend; \
fi
# Explicitly make _depend in subdirs containing multiple targets to prevent
# parallel sub-makes creating .depend files simultaneously.
depend dep: $(TIMESTAMP_FILE) $(VERSION_FILE) \
......@@ -638,8 +663,9 @@ depend dep: $(TIMESTAMP_FILE) $(VERSION_FILE) \
$(obj)include/autoconf.mk \
$(obj)include/generated/generic-asm-offsets.h \
$(obj)include/generated/asm-offsets.h
for dir in $(SUBDIRS) $(CPUDIR) $(LDSCRIPT_MAKEFILE_DIR) ; do \
$(MAKE) -C $$dir _depend ; done
+for dir in $(SUBDIRS) $(CPUDIR) $(LDSCRIPT_MAKEFILE_DIR) ; do \
$(call select_makefile2, $$dir); \
done
TAG_SUBDIRS = $(SUBDIRS)
TAG_SUBDIRS += $(dir $(__LIBS))
......
# our default target
.PHONY: all
all:
include $(TOPDIR)/config.mk
LIB := $(obj)built-in.o
LIBGCC = $(obj)libgcc.o
SRCS :=
include Makefile
# Backward compatible: obj-y is preferable
COBJS := $(sort $(COBJS) $(COBJS-y))
SOBJS := $(sort $(SOBJS) $(SOBJS-y))
# Going forward use the following
obj-y := $(sort $(obj-y))
extra-y := $(sort $(extra-y))
lib-y := $(sort $(lib-y))
SRCS += $(COBJS:.o=.c) $(SOBJS:.o=.S) \
$(wildcard $(obj-y:.o=.c) $(obj-y:.o=.S) $(lib-y:.o=.c) $(lib-y:.o=.S) $(extra-y:.o=.c) $(extra-y:.o=.S))
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS) $(obj-y))
LGOBJS := $(addprefix $(obj),$(sort $(GLSOBJS) $(GLCOBJS)) $(lib-y))
all: $(LIB) $(addprefix $(obj),$(extra-y))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
ifneq ($(strip $(lib-y)),)
all: $(LIBGCC)
$(LIBGCC): $(obj).depend $(LGOBJS)
$(call cmd_link_o_target, $(LGOBJS))
endif
#########################################################################
# defines $(obj).depend target
include $(TOPDIR)/rules.mk
sinclude $(obj).depend
#########################################################################
......@@ -200,11 +200,29 @@ GEN_UBOOT = \
$(obj)$(SPL_BIN): depend $(START) $(LIBS) $(obj)u-boot-spl.lds
$(GEN_UBOOT)
# Tentative step for Kbuild-style makefiles coexist with conventional U-Boot style makefiles
# U-Boot conventional sub makefiles always include some other makefiles.
# So, the build system searches a line beginning with "include" before entering into the sub makefile
# in order to distinguish which style it is.
# If the Makefile include a "include" line, we assume it is an U-Boot style makefile.
# Otherwise, it is treated as a Kbuild-style makefile.
select_makefile = \
if grep -q "^include" $1/Makefile; then \
$(MAKE) -C $1; \
else \
$(MAKE) -C $1 -f $(TOPDIR)/scripts/Makefile.build; \
mv $(dir $@)built-in.o $@; \
fi
# We do not need to build $(START) explicitly.
# It is built while we are at $(CPUDIR)/lib$(CPU).o build.
$(START): depend
$(MAKE) -C $(SRCTREE)/$(START_PATH) $@
if grep -q "^include" $(SRCTREE)$(dir $(subst $(SPLTREE),,$@))Makefile; then \
$(MAKE) -C $(SRCTREE)/$(START_PATH) $@; \
fi
$(LIBS): depend
$(MAKE) -C $(SRCTREE)$(dir $(subst $(SPLTREE),,$@))
+$(call select_makefile, $(SRCTREE)$(dir $(subst $(SPLTREE),,$@)))
$(obj)u-boot-spl.lds: $(LDSCRIPT) depend
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj). -ansi -D__ASSEMBLY__ -P - < $< > $@
......
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