Skip to content
  • Haibo Chen's avatar
    mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON when necessary · 925f6900
    Haibo Chen authored and Jaehoon Chung's avatar Jaehoon Chung committed
    After commit f132aab4
    
     ("Revert "mmc: fsl_esdhc_imx: use
    VENDORSPEC_FRC_SDCLK_ON to control card clock output""), it
    involve issue in mmc_switch_voltage(), because of the special
    design of usdhc.
    
    For FSL_USDHC, it do not implement VENDORSPEC_CKEN/PEREN/HCKEN/IPGEN,
    these are reserved bits(Though RM contain the definition of these bits,
    but actually internal IC logic do not implement, already confirm with
    IC team). Instead, use VENDORSPEC_FRC_SDCLK_ON to gate on/off the card
    clock output. Here is the definition of this bit in RM:
    
    [8] FRC_SDCLK_ON
    Force CLK output active
    Do not set this bit to 1 unless it is necessary. Also, make sure that
    this bit is cleared when uSDHC’s clock is about to be changed (frequency
    change, clock source change, or delay chain tuning).
    0b - CLK active or inactive is fully controlled by the hardware.
    1b - Force CLK active
    
    In default, the FRC_SDCLK_ON is 0. This means, when there is no command
    or data transfer on bus, hardware will gate off the card clock. But in
    some case, we need the card clock keep on. Take IO voltage 1.8v switch
    as example, after IO voltage change to 1.8v, spec require gate off the
    card clock for 5ms, and gate on the clock back, once detect the card
    clock on, then the card will draw the dat0 to high immediately. If there
    is not clock gate off/on behavior, some card will keep the dat0 to low
    level. This is the reason we fail in mmc_switch_voltage().
    
    To fix this issue, and concern that this is only the fsl usdhc hardware
    design limitation, set the bit FRC_SDCLK_ON in the beginning of the
    wait_dat0() and clear it in the end. To make sure the 1.8v IO voltage
    switch process align with SD specification.
    
    For standard tuning process, usdhc specification also require the card
    clock keep on, so also add these behavior in fsl_esdhc_execute_tuning().
    
    Reviewed-by: default avatarMarek Vasut <marex@denx.de>
    Tested-by: default avatarFabio Estevam <festevam@gmail.com>
    Signed-off-by: default avatarHaibo Chen <haibo.chen@nxp.com>
    Reviewed-by: Peng Fan's avatarPeng Fan <peng.fan@nxp.com>
    Reviewed-by: default avatarJaehoon Chung <jh80.chung@samsung.com>
    925f6900