Commit d77fa2ff authored by Tom Rini's avatar Tom Rini

Merge http://git.denx.de/u-boot-samsung

Signed-off-by: Tom Rini's avatarTom Rini <trini@konsulko.com>

Conflicts:
	configs/peach-pi_defconfig
	configs/peach-pit_defconfig
parents 65eac4cc 086e13c5
......@@ -442,7 +442,6 @@ config TARGET_BCMNSP
config ARCH_EXYNOS
bool "Samsung EXYNOS"
select CPU_V7
select DM
select DM_SPI_FLASH
select DM_SERIAL
......
......@@ -12,6 +12,9 @@
#include <asm/io.h>
#include <asm/arch/pwm.h>
#include <asm/arch/clk.h>
/* Use the old PWM interface for now */
#undef CONFIG_DM_PWM
#include <pwm.h>
DECLARE_GLOBAL_DATA_PTR;
......
......@@ -21,6 +21,7 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
exynos5420-peach-pit.dtb \
exynos5800-peach-pi.dtb \
exynos5422-odroidxu3.dtb
dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-firefly.dtb \
rk3288-jerry.dtb \
......
......@@ -163,13 +163,14 @@
};
fimd@14400000 {
u-boot,dm-pre-reloc;
compatible = "samsung,exynos-fimd";
reg = <0x14400000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
};
dp@145b0000 {
dp: dp@145b0000 {
compatible = "samsung,exynos5-dp";
reg = <0x145b0000 0x1000>;
#address-cells = <1>;
......
......@@ -198,6 +198,20 @@
reset-gpios = <&gpx1 5 GPIO_ACTIVE_LOW>;
hotplug-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>;
edid-emulation = <5>;
ports {
port@0 {
bridge_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
port@1 {
bridge_in: endpoint {
remote-endpoint = <&dp_out>;
};
};
};
};
soundcodec@22 {
......@@ -223,6 +237,27 @@
};
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm 0 1000000 0>;
brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
default-brightness-level = <7>;
enable-gpios = <&gpx3 0 GPIO_ACTIVE_HIGH>;
power-supply = <&fet1>;
};
panel: panel {
compatible = "auo,b116xw03";
power-supply = <&fet6>;
backlight = <&backlight>;
port {
panel_in: endpoint {
remote-endpoint = <&bridge_out>;
};
};
};
spi@131b0000 {
spi-max-frequency = <1000000>;
spi-deactivate-delay = <100>;
......@@ -337,6 +372,15 @@
samsung,dynamic-range = <0>;
samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>;
samsung,hpd-gpio = <&gpx0 7 GPIO_ACTIVE_HIGH>;
ports {
port@0 {
dp_out: endpoint {
remote-endpoint = <&bridge_in>;
};
};
};
};
};
......
......@@ -158,6 +158,27 @@
samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm 0 1000000 0>;
brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
default-brightness-level = <1>;
enable-gpios = <&gpx3 0 GPIO_ACTIVE_HIGH>;
power-supply = <&fet1>;
};
panel: panel {
compatible = "auo,b116xw03";
power-supply = <&fet6>;
backlight = <&backlight>;
port {
panel_in: endpoint {
remote-endpoint = <&bridge_out>;
};
};
};
};
&i2c_0 {
......@@ -385,6 +406,25 @@
};
};
&dp {
status = "okay";
samsung,color-space = <0>;
samsung,dynamic-range = <0>;
samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>;
samsung,link-rate = <0x0a>;
samsung,lane-count = <1>;
samsung,hpd-gpio = <&gpc3 0 GPIO_ACTIVE_HIGH>;
ports {
port@0 {
dp_out: endpoint {
remote-endpoint = <&bridge_in>;
};
};
};
};
&i2c_1 {
status = "okay";
samsung,i2c-sda-delay = <100>;
......@@ -585,6 +625,19 @@
0x04 0x59 0x60 /* MPU Clock source: LC => RCO */
0x04 0x54 0x14 /* LC -> RCO */
0x02 0xa1 0x91>; /* HPD high */
ports {
port@0 {
bridge_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
port@1 {
bridge_in: endpoint {
remote-endpoint = <&dp_out>;
};
};
};
};
soundcodec@20 {
......
......@@ -116,4 +116,11 @@
};
};
pwm: pwm@12dd0000 {
compatible = "samsung,exynos4210-pwm";
reg = <0x12dd0000 0x100>;
samsung,pwm-outputs = <0>, <1>, <2>, <3>;
#pwm-cells = <3>;
};
};
......@@ -9,6 +9,8 @@
/dts-v1/;
#include "exynos54xx.dtsi"
#include <dt-bindings/clock/maxim,max77802.h>
#include <dt-bindings/regulator/maxim,max77802.h>
/ {
model = "Samsung/Google Peach Pit board based on Exynos5420";
......@@ -29,6 +31,14 @@
i2c104 = &i2c_tunnel;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm 0 1000000 0>;
brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
default-brightness-level = <7>;
power-supply = <&tps65090_fet1>;
};
dmc {
mem-manuf = "samsung";
mem-type = "ddr3";
......@@ -188,6 +198,20 @@
0x04 0x59 0x60
0x04 0x54 0x14 /* LC -> RCO */
0x02 0xa1 0x91>; /* HPD high */
ports {
port@0 {
bridge_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
port@1 {
bridge_in: endpoint {
remote-endpoint = <&dp_out>;
};
};
};
};
};
......@@ -203,6 +227,18 @@
};
};
panel: panel {
compatible = "auo,b116xw03";
power-supply = <&tps65090_fet6>;
backlight = <&backlight>;
port {
panel_in: endpoint {
remote-endpoint = <&bridge_out>;
};
};
};
spi@12d30000 { /* spi1 */
spi-max-frequency = <50000000>;
firmware_storage_spi: flash@0 {
......@@ -254,6 +290,25 @@
};
};
&dp {
status = "okay";
samsung,color-space = <0>;
samsung,dynamic-range = <0>;
samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>;
samsung,link-rate = <0x06>;
samsung,lane-count = <2>;
samsung,hpd-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>;
ports {
port@0 {
dp_out: endpoint {
remote-endpoint = <&bridge_in>;
};
};
};
};
&spi_2 {
spi-max-frequency = <3125000>;
spi-deactivate-delay = <200>;
......
......@@ -49,7 +49,7 @@
status = "disabled";
};
i2c@12CA0000 {
hsi2c_4: i2c@12CA0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,exynos5-hsi2c";
......@@ -178,7 +178,7 @@
samsung,pwm-out-gpio = <&gpb2 0 GPIO_ACTIVE_HIGH>;
};
dp@145b0000 {
dp: dp@145b0000 {
samsung,lt-status = <0>;
samsung,master-mode = <0>;
......@@ -197,6 +197,13 @@
mem-type = "ddr3";
};
pwm: pwm@12dd0000 {
compatible = "samsung,exynos4210-pwm";
reg = <0x12dd0000 0x100>;
samsung,pwm-outputs = <0>, <1>, <2>, <3>;
#pwm-cells = <3>;
};
xhci1: xhci@12400000 {
compatible = "samsung,exynos5250-xhci";
reg = <0x12400000 0x10000>;
......
......@@ -30,6 +30,27 @@
i2c104 = &i2c_tunnel;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm 0 1000000 0>;
brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
default-brightness-level = <7>;
enable-gpios = <&gpx2 2 GPIO_ACTIVE_HIGH>;
power-supply = <&tps65090_fet1>;
};
panel: panel {
compatible = "auo,b133htn01";
power-supply = <&tps65090_fet6>;
backlight = <&backlight>;
port {
panel_in: endpoint {
remote-endpoint = <&dp_out>;
};
};
};
dmc {
mem-manuf = "samsung";
mem-type = "ddr3";
......@@ -132,6 +153,25 @@
};
};
&dp {
status = "okay";
samsung,color-space = <0>;
samsung,dynamic-range = <0>;
samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>;
samsung,link-rate = <0x0a>;
samsung,lane-count = <2>;
samsung,hpd-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>;
ports {
port {
dp_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
};
&spi_2 {
spi-max-frequency = <3125000>;
spi-deactivate-delay = <200>;
......
/*
* Samsung Espresso7420 board device tree source
*
* Copyright (c) 2016 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include "exynos7420.dtsi"
/ {
model = "Samsung Espresso7420 board based on Exynos7420";
compatible = "samsung,espresso7420", "samsung,exynos7420";
aliases {
serial2 = "/serial@14C30000";
console = "/serial@14C30000";
pinctrl0 = "/pinctrl@13470000";
};
};
&fin_pll {
clock-frequency = <24000000>;
};
/*
* Samsung Exynos7420 SoC device tree source
*
* Copyright (c) 2016 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "skeleton.dtsi"
#include <dt-bindings/clock/exynos7420-clk.h>
/ {
compatible = "samsung,exynos7420";
fin_pll: xxti {
compatible = "fixed-clock";
clock-output-names = "fin_pll";
u-boot,dm-pre-reloc;
#clock-cells = <0>;
};
clock_topc: clock-controller@10570000 {
compatible = "samsung,exynos7-clock-topc";
reg = <0x10570000 0x10000>;
u-boot,dm-pre-reloc;
#clock-cells = <1>;
clocks = <&fin_pll>;
clock-names = "fin_pll";
};
clock_top0: clock-controller@105d0000 {
compatible = "samsung,exynos7-clock-top0";
reg = <0x105d0000 0xb000>;
u-boot,dm-pre-reloc;
#clock-cells = <1>;
clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
<&clock_topc DOUT_SCLK_BUS1_PLL>,
<&clock_topc DOUT_SCLK_CC_PLL>,
<&clock_topc DOUT_SCLK_MFC_PLL>;
clock-names = "fin_pll", "dout_sclk_bus0_pll",
"dout_sclk_bus1_pll", "dout_sclk_cc_pll",
"dout_sclk_mfc_pll";
};
clock_peric1: clock-controller@14c80000 {
compatible = "samsung,exynos7-clock-peric1";
reg = <0x14c80000 0xd00>;
u-boot,dm-pre-reloc;
#clock-cells = <1>;
clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>,
<&clock_top0 CLK_SCLK_UART1>,
<&clock_top0 CLK_SCLK_UART2>,
<&clock_top0 CLK_SCLK_UART3>;
clock-names = "fin_pll", "dout_aclk_peric1_66",
"sclk_uart1", "sclk_uart2", "sclk_uart3";
};
pinctrl@13470000 {
compatible = "samsung,exynos7420-pinctrl";
reg = <0x13470000 0x1000>;
u-boot,dm-pre-reloc;
serial2_bus: serial2-bus {
samsung,pins = "gpd1-4", "gpd1-5";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
u-boot,dm-pre-reloc;
};
};
serial@14C30000 {
compatible = "samsung,exynos4210-uart";
reg = <0x14C30000 0x100>;
u-boot,dm-pre-reloc;
clocks = <&clock_peric1 PCLK_UART2>,
<&clock_peric1 SCLK_UART2>;
clock-names = "uart", "clk_uart_baud0";
pinctrl-names = "default";
pinctrl-0 = <&serial2_bus>;
};
};
if ARCH_EXYNOS
choice
prompt "EXYNOS board select"
prompt "EXYNOS architecture type select"
optional
config ARCH_EXYNOS4
bool "Exynos4 SoC family"
select CPU_V7
help
Samsung Exynos4 SoC family are based on ARM Cortex-A9 CPU. There
are multiple SoCs in this family including Exynos4210, Exynos4412,
and Exynos4212.
config ARCH_EXYNOS5
bool "Exynos5 SoC family"
select CPU_V7
help
Samsung Exynos5 SoC family are based on ARM Cortex-A15 CPU (and
Cortex-A7 CPU in big.LITTLE configuration). There are multiple SoCs
in this family including Exynos5250, Exynos5420 and Exynos5800.
config ARCH_EXYNOS7
bool "Exynos7 SoC family"
select ARM64
help
Samsung Exynos7 SoC family are based on ARM Cortex-A57 CPU or
Cortex-A53 CPU (and some in a big.LITTLE configuration). There are
multiple SoCs in this family including Exynos7420.
endchoice
if ARCH_EXYNOS4
choice
prompt "EXYNOS4 board select"
config TARGET_SMDKV310
select SUPPORT_SPL
bool "Exynos4210 SMDKV310 board"
......@@ -25,6 +56,14 @@ config TARGET_TRATS2
config TARGET_ODROID
bool "Exynos4412 Odroid board"
endchoice
endif
if ARCH_EXYNOS5
choice
prompt "EXYNOS5 board select"
config TARGET_ODROID_XU3
bool "Exynos5422 Odroid board"
select OF_CONTROL
......@@ -68,6 +107,25 @@ config TARGET_PEACH_PIT
select OF_CONTROL
endchoice
endif
if ARCH_EXYNOS7
choice
prompt "EXYNOS7 board select"
config TARGET_ESPRESSO7420
bool "ESPRESSO7420 board"
select ARM64
select SUPPORT_SPL
select OF_CONTROL
select SPL_DISABLE_OF_CONTROL
select PINCTRL
select PINCTRL_EXYNOS7420
select CLK_EXYNOS
endchoice
endif
config SYS_SOC
default "exynos"
......@@ -81,5 +139,6 @@ source "board/samsung/odroid/Kconfig"
source "board/samsung/arndale/Kconfig"
source "board/samsung/smdk5250/Kconfig"
source "board/samsung/smdk5420/Kconfig"
source "board/samsung/espresso7420/Kconfig"
endif
......@@ -5,7 +5,9 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += clock.o power.o soc.o system.o pinmux.o tzpc.o
obj-y += soc.o
obj-$(CONFIG_CPU_V7) += clock.o pinmux.o power.o system.o
obj-$(CONFIG_ARM64) += mmu-arm64.o
obj-$(CONFIG_EXYNOS5420) += sec_boot.o
......@@ -13,6 +15,6 @@ ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_EXYNOS5) += clock_init_exynos5.o
obj-$(CONFIG_EXYNOS5) += dmc_common.o dmc_init_ddr3.o
obj-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o
obj-y += spl_boot.o
obj-y += spl_boot.o tzpc.o
obj-y += lowlevel_init.o
endif
......@@ -270,7 +270,7 @@ IS_EXYNOS_TYPE(exynos5420, 0x5420)
IS_EXYNOS_TYPE(exynos5422, 0x5422)
#define SAMSUNG_BASE(device, base) \
static inline unsigned int __attribute__((no_instrument_function)) \
static inline unsigned long __attribute__((no_instrument_function)) \
samsung_get_base_##device(void) \
{ \
if (cpu_is_exynos4()) { \
......@@ -288,9 +288,7 @@ static inline unsigned int __attribute__((no_instrument_function)) \
SAMSUNG_BASE(adc, ADC_BASE)
SAMSUNG_BASE(clock, CLOCK_BASE)
SAMSUNG_BASE(ace_sfr, ACE_SFR_BASE)
SAMSUNG_BASE(dp, DP_BASE)
SAMSUNG_BASE(sysreg, SYSREG_BASE)
SAMSUNG_BASE(fimd, FIMD_BASE)
SAMSUNG_BASE(i2c, I2C_BASE)
SAMSUNG_BASE(i2s, I2S_BASE)
SAMSUNG_BASE(mipi_dsim, MIPI_DSIM_BASE)
......
......@@ -61,7 +61,7 @@ struct edp_video_info {
unsigned int color_depth;
};
struct edp_device_info {
struct exynos_dp_priv {
struct edp_disp_info disp_info;
struct edp_link_train_info lt_info;
struct edp_video_info video_info;
......@@ -72,6 +72,7 @@ struct edp_device_info {
unsigned char dpcd_rev;
/*support enhanced frame cap */
unsigned char dpcd_efc;
struct exynos_dp *regs;
};
enum analog_power_block {
......@@ -185,7 +186,7 @@ enum {
struct exynos_dp_platform_data {
struct edp_device_info *edp_dev_info;
struct exynos_dp_priv *edp_dev_info;
};
#ifdef CONFIG_EXYNOS_DP
......
......@@ -1349,7 +1349,7 @@ enum exynos5420_gpio_pin {
};
struct gpio_info {
unsigned int reg_addr; /* Address of register for this part */
unsigned long reg_addr; /* Address of register for this part */
unsigned int max_gpio; /* Maximum GPIO in this part */
};
......
......@@ -320,7 +320,7 @@ struct mipi_dsim_lcd_device {
int reverse_panel;
struct mipi_dsim_device *master;
void *platform_data;
struct exynos_platform_mipi_dsim *platform_data;
};
/*
......@@ -347,9 +347,10 @@ struct mipi_dsim_lcd_driver {
};
#ifdef CONFIG_EXYNOS_MIPI_DSIM
int exynos_mipi_dsi_init(void);
int exynos_mipi_dsi_init(struct exynos_platform_mipi_dsim *dsim_pd);
#else
static inline int exynos_mipi_dsi_init(void)
static inline int exynos_mipi_dsi_init(
struct exynos_platform_mipi_dsim *dsim_pd)
{
return 0;
}
......@@ -369,7 +370,8 @@ int exynos_mipi_dsi_register_lcd_device(struct mipi_dsim_lcd_device
*lcd_dev);
void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd);
void exynos_init_dsim_platform_data(vidinfo_t *vid);
struct vidinfo;
void exynos_init_dsim_platform_data(struct vidinfo *vid);
/* panel driver init based on mipi dsi interface */
void s6e8ax0_init(void);
......
......@@ -1717,7 +1717,7 @@ void set_usbdrd_phy_ctrl(unsigned int enable);
#define POWER_USB_DRD_PHY_CTRL_EN (1 << 0)
#define POWER_USB_DRD_PHY_CTRL_DISABLE (0 << 0)
void set_dp_phy_ctrl(unsigned int enable);
void exynos_dp_phy_ctrl(unsigned int enable);
#define EXYNOS_DP_PHY_ENABLE (1 << 0)
......
......@@ -216,8 +216,11 @@ int do_lowlevel_init(void)
if (actions & DO_CLOCKS) {
system_clock_init();
#ifdef CONFIG_DEBUG_UART
#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT)) || \
!defined(CONFIG_SPL_BUILD)
exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
debug_uart_init();
#endif
#endif
mem_ctrl_init(actions & DO_MEM_RESET);
tzpc_init();
......
/*
* Copyright (C) 2016 Samsung Electronics
* Thomas Abraham <thomas.ab@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/armv8/mmu.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_EXYNOS7420
static struct mm_region exynos7420_mem_map[] = {
{
.base = 0x10000000UL,
.size = 0x10000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN,
}, {