Commit c8e743c1 authored by Jagan Teki's avatar Jagan Teki

clk: sunxi: Add Allwinner A10s/A13 CLK driver

Add initial clock driver for Allwinner A10s/A13.

- Implement USB ahb and USB clocks via ccu_clk_gate table
  for A10s/A13, so it can accessed in common clk enable and
  disable functions from clk_sunxi.c
- Implement USB resets via ccu_reset table for A10s/A13,
  so it can accessed in common reset deassert and assert
  functions from reset-sunxi.c
Signed-off-by: Jagan Teki's avatarJagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard's avatarMaxime Ripard <maxime.ripard@bootlin.com>
parent 6590bd8c
...@@ -16,6 +16,13 @@ config CLK_SUN4I_A10 ...@@ -16,6 +16,13 @@ config CLK_SUN4I_A10
This enables common clock driver support for platforms based This enables common clock driver support for platforms based
on Allwinner A10/A20 SoC. on Allwinner A10/A20 SoC.
config CLK_SUN5I_A10S
bool "Clock driver for Allwinner A10s/A13"
default MACH_SUN5I
help
This enables common clock driver support for platforms based
on Allwinner A10s/A13 SoC.
config CLK_SUN8I_H3 config CLK_SUN8I_H3
bool "Clock driver for Allwinner H3/H5" bool "Clock driver for Allwinner H3/H5"
default MACH_SUNXI_H3_H5 default MACH_SUNXI_H3_H5
......
...@@ -7,5 +7,6 @@ ...@@ -7,5 +7,6 @@
obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o
obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o
obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o
obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2018 Amarula Solutions.
* Author: Jagan Teki <jagan@amarulasolutions.com>
*/
#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
#include <asm/arch/ccu.h>
#include <dt-bindings/clock/sun5i-ccu.h>
#include <dt-bindings/reset/sun5i-ccu.h>
static struct ccu_clk_gate a10s_gates[] = {
[CLK_AHB_OTG] = GATE(0x060, BIT(0)),
[CLK_AHB_EHCI] = GATE(0x060, BIT(1)),
[CLK_AHB_OHCI] = GATE(0x060, BIT(2)),
[CLK_USB_OHCI] = GATE(0x0cc, BIT(6)),
[CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
[CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
};
static struct ccu_reset a10s_resets[] = {
[RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
[RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
};
static const struct ccu_desc a10s_ccu_desc = {
.gates = a10s_gates,
.resets = a10s_resets,
};
static int a10s_clk_bind(struct udevice *dev)
{
return sunxi_reset_bind(dev, ARRAY_SIZE(a10s_resets));
}
static const struct udevice_id a10s_ccu_ids[] = {
{ .compatible = "allwinner,sun5i-a10s-ccu",
.data = (ulong)&a10s_ccu_desc },
{ .compatible = "allwinner,sun5i-a13-ccu",
.data = (ulong)&a10s_ccu_desc },
{ }
};
U_BOOT_DRIVER(clk_sun5i_a10s) = {
.name = "sun5i_a10s_ccu",
.id = UCLASS_CLK,
.of_match = a10s_ccu_ids,
.priv_auto_alloc_size = sizeof(struct ccu_priv),
.ops = &sunxi_clk_ops,
.probe = sunxi_clk_probe,
.bind = a10s_clk_bind,
};
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