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As noted in commit 3a638320 ("mmc: sdhci: add the quirk for broken r1b response"), some MMC controllers don't always set the transfer complete bit with R1b responses. According to the SD Host Controller Simplified Specification v4.20, > In the case of a command pairing with response-with-busy[, Transfer > Complete] is set when busy is de-asserted. Refer to DAT Line Active > and Command Inhibit (DAT) in the Present State register. By polling the DAT Line Active bit in the present state register, we can detect when we are no longer busy, without waiting for a long timeout. This results in much faster reads/writes on buggy controllers. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Tested-by: Henrik Grimler <henrik@grimler.se>
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