Commit 30e71ad5 authored by Lothar Felten's avatar Lothar Felten Committed by Jagan Teki

sunxi: R40: add gigabit ethernet clocks

Add clock control entries for the gigabit interface of the Allwinner
R40/V40 CPU
Acked-by: Maxime Ripard's avatarMaxime Ripard <>
Reviewed-by: Joe Hershberger's avatarJoe Hershberger <>
Reviewed-by: default avatarJagan Teki <>
Tested-by: default avatarJagan Teki <>
Signed-off-by: default avatarLothar Felten <>
parent df63fcc0
......@@ -60,7 +60,11 @@ struct sunxi_ccm_reg {
u32 reserved11;
u32 sata_clk_cfg; /* 0xc8 SATA clock control (R40 only) */
u32 usb_clk_cfg; /* 0xcc USB clock control */
u32 gmac_clk_cfg; /* 0xd0 GMAC clock control */
u32 cir0_clk_cfg; /* 0xd0 CIR0 clock control (R40 only) */
u32 gmac_clk_cfg; /* 0xd0 GMAC clock control (not for R40) */
u32 reserved12[7];
u32 mdfs_clk_cfg; /* 0xf0 MDFS clock control */
u32 dram_clk_cfg; /* 0xf4 DRAM configuration clock control */
......@@ -103,7 +107,11 @@ struct sunxi_ccm_reg {
u32 mtc_clk_cfg; /* 0x158 MTC module clock */
u32 mbus0_clk_cfg; /* 0x15c MBUS0 module clock */
u32 mbus1_clk_cfg; /* 0x160 MBUS1 module clock */
u32 gmac_clk_cfg; /* 0x164 GMAC clock control (R40 only) */
u32 reserved16;
u32 mipi_dsi_clk_cfg; /* 0x168 MIPI DSI clock control */
u32 mipi_csi_clk_cfg; /* 0x16c MIPI CSI clock control */
u32 reserved17[4];
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment