Commit 73aede59 authored by Ley Foon Tan's avatar Ley Foon Tan Committed by Marek Vasut

arm: socfpga: stratix10: Add timer support for Stratix10 SoC

Add timer support for Stratix SoC
Signed-off-by: default avatarChin Liang See <chin.liang.see@intel.com>
Signed-off-by: default avatarLey Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Marek Vasut's avatarMarek Vasut <marex@denx.de>
parent 4765ddb0
......@@ -9,7 +9,6 @@ obj-y += board.o
obj-y += clock_manager.o
obj-y += misc.o
obj-y += reset_manager.o
obj-y += timer.o
ifdef CONFIG_TARGET_SOCFPGA_GEN5
obj-y += clock_manager_gen5.o
......@@ -17,6 +16,7 @@ obj-y += misc_gen5.o
obj-y += reset_manager_gen5.o
obj-y += scan_manager.o
obj-y += system_manager_gen5.o
obj-y += timer.o
obj-y += wrap_pll_config.o
obj-y += fpga_manager.o
endif
......@@ -26,6 +26,7 @@ obj-y += clock_manager_arria10.o
obj-y += misc_arria10.o
obj-y += pinmux_arria10.o
obj-y += reset_manager_arria10.o
obj-y += timer.o
endif
ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
......@@ -35,6 +36,7 @@ obj-y += misc_s10.o
obj-y += mmu-arm64_s10.o
obj-y += reset_manager_s10.o
obj-y += system_manager_s10.o
obj-y += timer_s10.o
obj-y += wrap_pinmux_config_s10.o
obj-y += wrap_pll_config_s10.o
endif
......
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
*
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/timer.h>
/*
* Timer initialization
*/
int timer_init(void)
{
int enable = 0x3; /* timer enable + output signal masked */
int loadval = ~0;
/* enable system counter */
writel(enable, SOCFPGA_GTIMER_SEC_ADDRESS);
/* enable processor pysical counter */
asm volatile("msr cntp_ctl_el0, %0" : : "r" (enable));
asm volatile("msr cntp_tval_el0, %0" : : "r" (loadval));
return 0;
}
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