Commit 7514ed33 authored by Andre Przywara's avatar Andre Przywara Committed by Jagan Teki

sunxi: DT: update device tree files for Allwinner H3 and H5 SoCs

Update the device tree files from the Linux tree as of v4.18-rc3,
exactly Linux commit:
commit 55c5ba5e49a0a124ed416880e8227b493474495e
Author: Chen-Yu Tsai <wens@csie.org>
Date:   Tue Apr 24 19:34:22 2018 +0800

    arm64: dts: allwinner: h5: Add cpu0 label for first cpu

Since the H3 and H5 are very similar (aside from the actual ARM cores),
they share most the SoC .dtsi and thus have to be updated together.
One tiny change is the removal of the "arm/" prefix from the include
path in the sun50i-h5.dtsi, which is needed because we don't share the
same sophisticated DT directory layout of Linux.
Also we need to fix up the board .dts files already, since the .dtsi
removes some pins, so the .dts can't reference them anymore. This is to
maintain bisectability.
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard's avatarMaxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Jagan Teki's avatarJagan Teki <jagan@amarulasolutions.com>
parent 68dd17c3
......@@ -72,8 +72,6 @@
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
......
......@@ -71,8 +71,6 @@
compatible = "allwinner,sun50i-h5-mmc",
"allwinner,sun50i-a64-mmc",
"allwinner,sun5i-a13-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
......
......@@ -100,8 +100,6 @@
compatible = "allwinner,sun50i-h5-mmc",
"allwinner,sun50i-a64-mmc",
"allwinner,sun5i-a13-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
......
......@@ -84,8 +84,6 @@
compatible = "allwinner,sun50i-h5-mmc",
"allwinner,sun50i-a64-mmc",
"allwinner,sun5i-a13-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
......
......@@ -71,8 +71,6 @@
compatible = "allwinner,sun50i-h5-mmc",
"allwinner,sun50i-a64-mmc",
"allwinner,sun5i-a13-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
......
/*
* Copyright (c) 2016 ARM Ltd.
* Copyright (C) 2016 ARM Ltd.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
......@@ -40,24 +40,38 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "sun8i-h3.dtsi"
#include <sunxi-h3-h5.dtsi>
/ {
cpus {
cpu@0 {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0>;
enable-method = "psci";
};
cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <1>;
enable-method = "psci";
};
cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <2>;
enable-method = "psci";
};
cpu@3 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <3>;
enable-method = "psci";
};
};
......@@ -69,6 +83,14 @@
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
};
......@@ -76,8 +98,8 @@
compatible = "allwinner,sun50i-h5-ccu";
};
&gic {
compatible = "arm,gic-400";
&display_clocks {
compatible = "allwinner,sun50i-h5-de2-clk";
};
&mmc0 {
......@@ -104,6 +126,6 @@
&pio {
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
compatible = "allwinner,sun50i-h5-pinctrl";
};
......@@ -107,8 +107,6 @@
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
......@@ -117,8 +115,6 @@
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins_a>;
vmmc-supply = <&reg_vcc_wifi>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
......
......@@ -112,8 +112,6 @@
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
......@@ -122,8 +120,6 @@
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
vqmmc-supply = <&reg_vcc3v3>;
mmc-pwrseq = <&wifi_pwrseq>;
......@@ -193,7 +189,7 @@
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins_a>;
pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
status = "okay";
};
......
......@@ -76,8 +76,6 @@
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
......
......@@ -97,8 +97,6 @@
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
cd-inverted;
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
status = "okay";
vmmc-supply = <&reg_vcc3v3>;
};
......
......@@ -124,8 +124,6 @@
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
......@@ -134,8 +132,6 @@
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
......
......@@ -107,8 +107,6 @@
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
......@@ -117,8 +115,6 @@
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
non-removable;
......
......@@ -103,8 +103,6 @@
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
......
......@@ -54,8 +54,6 @@
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
non-removable;
......
......@@ -110,8 +110,6 @@
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
......
This diff is collapsed.
This diff is collapsed.
......@@ -131,8 +131,6 @@
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc_io>;
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
......
/*
* Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.io>
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
#ifndef _DT_BINDINGS_CLOCK_SUN8I_DE2_H_
#define _DT_BINDINGS_CLOCK_SUN8I_DE2_H_
#define CLK_BUS_MIXER0 0
#define CLK_BUS_MIXER1 1
#define CLK_BUS_WB 2
#define CLK_MIXER0 6
#define CLK_MIXER1 7
#define CLK_WB 8
#endif /* _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ */
/*
* Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.io>
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
#ifndef _DT_BINDINGS_RESET_SUN8I_DE2_H_
#define _DT_BINDINGS_RESET_SUN8I_DE2_H_
#define RST_MIXER0 0
#define RST_MIXER1 1
#define RST_WB 2
#endif /* _DT_BINDINGS_RESET_SUN8I_DE2_H_ */
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