Commit 914bb7ea authored by Tom Rini's avatar Tom Rini

Merge branch 'master' of git://git.denx.de/u-boot-socfpga

- Update SPDX tag in arch/arm/mach-socfpga/spl_a10.c
Signed-off-by: Tom Rini's avatarTom Rini <trini@konsulko.com>
parents f2df46e5 aa529663
......@@ -759,10 +759,10 @@ config ARCH_SOCFPGA
bool "Altera SOCFPGA family"
select ARCH_EARLY_INIT_R
select ARCH_MISC_INIT
select CPU_V7A
select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select DM
select DM_SERIAL
select ENABLE_ARM_SOC_BOOT0_HOOK
select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select OF_CONTROL
select SPL_LIBCOMMON_SUPPORT
select SPL_LIBDISK_SUPPORT
......@@ -772,20 +772,22 @@ config ARCH_SOCFPGA
select SPL_OF_CONTROL
select SPL_SERIAL_SUPPORT
select SPL_DM_SERIAL
select SPL_RESET_SUPPORT
select SPL_SPI_FLASH_SUPPORT if SPL_SPI_SUPPORT
select SPL_SPI_SUPPORT if DM_SPI
select SPL_WATCHDOG_SUPPORT
select SUPPORT_SPL
select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
select SYS_NS16550
select SYS_THUMB_BUILD
select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select ARM64 if TARGET_SOCFPGA_STRATIX10
imply CMD_MTDPARTS
imply CRC32_VERIFY
imply DM_SPI
imply DM_SPI_FLASH
imply FAT_WRITE
imply HW_WATCHDOG
imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10
config ARCH_SUNXI
bool "Support sunxi (Allwinner) SoCs"
......
......@@ -34,6 +34,7 @@
name = "memory";
device_type = "memory";
reg = <0x0 0x40000000>; /* 1GB */
u-boot,dm-pre-reloc;
};
a10leds {
......
......@@ -36,8 +36,8 @@
memory {
device_type = "memory";
/* We expect the bootloader to fill in the reg */
reg = <0 0 0 0>;
reg = <0 0 0 0x80000000>; /* 2GB */
u-boot,dm-pre-reloc;
};
};
......
......@@ -20,6 +20,12 @@ config TARGET_SOCFPGA_GEN5
bool
select ALTERA_SDRAM
config TARGET_SOCFPGA_STRATIX10
bool
select ARMV8_MULTIENTRY
select ARMV8_SPIN_TABLE
select ARMV8_SET_SMPEN
choice
prompt "Altera SOCFPGA board select"
optional
......@@ -57,6 +63,10 @@ config TARGET_SOCFPGA_SR1500
bool "SR1500 (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
config TARGET_SOCFPGA_STRATIX10_SOCDK
bool "Intel SOCFPGA SoCDK (Stratix 10)"
select TARGET_SOCFPGA_STRATIX10
config TARGET_SOCFPGA_TERASIC_DE0_NANO
bool "Terasic DE0-Nano-Atlas (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
......@@ -87,12 +97,14 @@ config SYS_BOARD
default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
default "sr1500" if TARGET_SOCFPGA_SR1500
default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
config SYS_VENDOR
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
......@@ -116,6 +128,7 @@ config SYS_CONFIG_NAME
default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
endif
......@@ -9,7 +9,6 @@ obj-y += board.o
obj-y += clock_manager.o
obj-y += misc.o
obj-y += reset_manager.o
obj-y += timer.o
ifdef CONFIG_TARGET_SOCFPGA_GEN5
obj-y += clock_manager_gen5.o
......@@ -17,6 +16,7 @@ obj-y += misc_gen5.o
obj-y += reset_manager_gen5.o
obj-y += scan_manager.o
obj-y += system_manager_gen5.o
obj-y += timer.o
obj-y += wrap_pll_config.o
obj-y += fpga_manager.o
endif
......@@ -26,23 +26,35 @@ obj-y += clock_manager_arria10.o
obj-y += misc_arria10.o
obj-y += pinmux_arria10.o
obj-y += reset_manager_arria10.o
obj-y += timer.o
endif
ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
obj-y += clock_manager_s10.o
obj-y += mailbox_s10.o
obj-y += misc_s10.o
obj-y += mmu-arm64_s10.o
obj-y += reset_manager_s10.o
obj-y += system_manager_s10.o
obj-y += timer_s10.o
obj-y += wrap_pinmux_config_s10.o
obj-y += wrap_pll_config_s10.o
endif
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
ifdef CONFIG_TARGET_SOCFPGA_GEN5
obj-y += spl_gen5.o
obj-y += freeze_controller.o
obj-y += wrap_iocsr_config.o
obj-y += wrap_pinmux_config.o
obj-y += wrap_sdram_config.o
endif
ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
obj-y += spl_a10.o
endif
ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
obj-y += spl_s10.o
endif
endif
ifdef CONFIG_TARGET_SOCFPGA_GEN5
......
......@@ -18,7 +18,20 @@
DECLARE_GLOBAL_DATA_PTR;
void s_init(void) {}
void s_init(void) {
#ifndef CONFIG_ARM64
/*
* Preconfigure ACTLR, make sure Write Full Line of Zeroes is disabled.
* This is optional on CycloneV / ArriaV.
* This is mandatory on Arria10, otherwise Linux refuses to boot.
*/
asm volatile(
"mcr p15, 0, %0, c1, c0, 1\n"
"isb\n"
"dsb\n"
::"r"(0x0));
#endif
}
/*
* Miscellaneous platform dependent initialisations
......
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
*
*/
#ifndef _FIREWALL_S10_
#define _FIREWALL_S10_
struct socfpga_firwall_l4_per {
u32 nand; /* 0x00 */
u32 nand_data;
u32 _pad_0x8;
u32 usb0;
u32 usb1; /* 0x10 */
u32 _pad_0x14;
u32 _pad_0x18;
u32 spim0;
u32 spim1; /* 0x20 */
u32 spis0;
u32 spis1;
u32 emac0;
u32 emac1; /* 0x30 */
u32 emac2;
u32 _pad_0x38;
u32 _pad_0x3c;
u32 sdmmc; /* 0x40 */
u32 gpio0;
u32 gpio1;
u32 _pad_0x4c;
u32 i2c0; /* 0x50 */
u32 i2c1;
u32 i2c2;
u32 i2c3;
u32 i2c4; /* 0x60 */
u32 timer0;
u32 timer1;
u32 uart0;
u32 uart1; /* 0x70 */
};
struct socfpga_firwall_l4_sys {
u32 _pad_0x00; /* 0x00 */
u32 _pad_0x04;
u32 dma_ecc;
u32 emac0rx_ecc;
u32 emac0tx_ecc; /* 0x10 */
u32 emac1rx_ecc;
u32 emac1tx_ecc;
u32 emac2rx_ecc;
u32 emac2tx_ecc; /* 0x20 */
u32 _pad_0x24;
u32 _pad_0x28;
u32 nand_ecc;
u32 nand_read_ecc; /* 0x30 */
u32 nand_write_ecc;
u32 ocram_ecc;
u32 _pad_0x3c;
u32 sdmmc_ecc; /* 0x40 */
u32 usb0_ecc;
u32 usb1_ecc;
u32 clock_manager;
u32 _pad_0x50; /* 0x50 */
u32 io_manager;
u32 reset_manager;
u32 system_manager;
u32 osc0_timer; /* 0x60 */
u32 osc1_timer;
u32 watchdog0;
u32 watchdog1;
u32 watchdog2; /* 0x70 */
u32 watchdog3;
};
#define FIREWALL_L4_DISABLE_ALL (BIT(0) | BIT(24) | BIT(16))
#define FIREWALL_BRIDGE_DISABLE_ALL (~0)
/* Cache coherency unit (CCU) registers */
#define CCU_CPU0_MPRT_ADBASE_DDRREG 0x4400
#define CCU_CPU0_MPRT_ADBASE_MEMSPACE0 0x45c0
#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1A 0x45e0
#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1B 0x4600
#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1C 0x4620
#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1D 0x4640
#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1E 0x4660
#define CCU_CPU0_MPRT_ADMASK_MEM_RAM0 0x4688
#define CCU_IOM_MPRT_ADBASE_MEMSPACE0 0x18560
#define CCU_IOM_MPRT_ADBASE_MEMSPACE1A 0x18580
#define CCU_IOM_MPRT_ADBASE_MEMSPACE1B 0x185a0
#define CCU_IOM_MPRT_ADBASE_MEMSPACE1C 0x185c0
#define CCU_IOM_MPRT_ADBASE_MEMSPACE1D 0x185e0
#define CCU_IOM_MPRT_ADBASE_MEMSPACE1E 0x18600
#define CCU_IOM_MPRT_ADMASK_MEM_RAM0 0x18628
#define CCU_ADMASK_P_MASK BIT(0)
#define CCU_ADMASK_NS_MASK BIT(1)
#define CCU_ADBASE_DI_MASK BIT(4)
#define CCU_REG_ADDR(reg) \
(SOCFPGA_CCU_ADDRESS + (reg))
/* Firewall MPU DDR SCR registers */
#define FW_MPU_DDR_SCR_EN 0x00
#define FW_MPU_DDR_SCR_EN_SET 0x04
#define FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT 0x18
#define FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT 0x1c
#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT 0x98
#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT 0x9c
#define MPUREGION0_ENABLE BIT(0)
#define NONMPUREGION0_ENABLE BIT(8)
#define FW_MPU_DDR_SCR_WRITEL(data, reg) \
writel(data, SOCFPGA_FW_MPU_DDR_SCR_ADDRESS + (reg))
#endif /* _FIREWALL_S10_ */
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
*
*/
#ifndef _MAILBOX_S10_H_
#define _MAILBOX_S10_H_
/* user define Uboot ID */
#define MBOX_CLIENT_ID_UBOOT 0xB
#define MBOX_ID_UBOOT 0x1
#define MBOX_CMD_DIRECT 0
#define MBOX_CMD_INDIRECT 1
#define MBOX_MAX_CMD_INDEX 2047
#define MBOX_CMD_BUFFER_SIZE 32
#define MBOX_RESP_BUFFER_SIZE 16
#define MBOX_HDR_CMD_LSB 0
#define MBOX_HDR_CMD_MSK (BIT(11) - 1)
#define MBOX_HDR_I_LSB 11
#define MBOX_HDR_I_MSK BIT(11)
#define MBOX_HDR_LEN_LSB 12
#define MBOX_HDR_LEN_MSK 0x007FF000
#define MBOX_HDR_ID_LSB 24
#define MBOX_HDR_ID_MSK 0x0F000000
#define MBOX_HDR_CLIENT_LSB 28
#define MBOX_HDR_CLIENT_MSK 0xF0000000
/* Interrupt flags */
#define MBOX_FLAGS_INT_COE BIT(0) /* COUT update interrupt enable */
#define MBOX_FLAGS_INT_RIE BIT(1) /* RIN update interrupt enable */
#define MBOX_FLAGS_INT_UAE BIT(8) /* Urgent ACK interrupt enable */
#define MBOX_ALL_INTRS (MBOX_FLAGS_INT_COE | \
MBOX_FLAGS_INT_RIE | \
MBOX_FLAGS_INT_UAE)
/* Status */
#define MBOX_STATUS_UA_MSK BIT(8)
#define MBOX_CMD_HEADER(client, id, len, indirect, cmd) \
((((cmd) << MBOX_HDR_CMD_LSB) & MBOX_HDR_CMD_MSK) | \
(((indirect) << MBOX_HDR_I_LSB) & MBOX_HDR_I_MSK) | \
(((len) << MBOX_HDR_LEN_LSB) & MBOX_HDR_LEN_MSK) | \
(((id) << MBOX_HDR_ID_LSB) & MBOX_HDR_ID_MSK) | \
(((client) << MBOX_HDR_CLIENT_LSB) & MBOX_HDR_CLIENT_MSK))
#define MBOX_RESP_ERR_GET(resp) \
(((resp) & MBOX_HDR_CMD_MSK) >> MBOX_HDR_CMD_LSB)
#define MBOX_RESP_LEN_GET(resp) \
(((resp) & MBOX_HDR_LEN_MSK) >> MBOX_HDR_LEN_LSB)
#define MBOX_RESP_ID_GET(resp) \
(((resp) & MBOX_HDR_ID_MSK) >> MBOX_HDR_ID_LSB)
#define MBOX_RESP_CLIENT_GET(resp) \
(((resp) & MBOX_HDR_CLIENT_MSK) >> MBOX_HDR_CLIENT_LSB)
/* Response error list */
enum ALT_SDM_MBOX_RESP_CODE {
/* CMD completed successfully, but check resp ARGS for any errors */
MBOX_RESP_STATOK = 0,
/* CMD is incorrectly formatted in some way */
MBOX_RESP_INVALID_COMMAND = 1,
/* BootROM Command code not undesrtood */
MBOX_RESP_UNKNOWN_BR = 2,
/* CMD code not recognized by firmware */
MBOX_RESP_UNKNOWN = 3,
/* Indicates that the device is not configured */
MBOX_RESP_NOT_CONFIGURED = 256,
/* Indicates that the device is busy */
MBOX_RESP_DEVICE_BUSY = 0x1FF,
/* Indicates that there is no valid response available */
MBOX_RESP_NO_VALID_RESP_AVAILABLE = 0x2FF,
/* General Error */
MBOX_RESP_ERROR = 0x3FF,
};
/* Mailbox command list */
#define MBOX_RESTART 2
#define MBOX_CONFIG_STATUS 4
#define MBOX_RECONFIG 6
#define MBOX_RECONFIG_MSEL 7
#define MBOX_RECONFIG_DATA 8
#define MBOX_RECONFIG_STATUS 9
#define MBOX_QSPI_OPEN 50
#define MBOX_QSPI_CLOSE 51
#define MBOX_QSPI_DIRECT 59
#define MBOX_REBOOT_HPS 71
/* Mailbox registers */
#define MBOX_CIN 0 /* command valid offset */
#define MBOX_ROUT 4 /* response output offset */
#define MBOX_URG 8 /* urgent command */
#define MBOX_FLAGS 0x0c /* interrupt enables */
#define MBOX_COUT 0x20 /* command free offset */
#define MBOX_RIN 0x24 /* respond valid offset */
#define MBOX_STATUS 0x2c /* mailbox status */
#define MBOX_CMD_BUF 0x40 /* circular command buffer */
#define MBOX_RESP_BUF 0xc0 /* circular response buffer */
#define MBOX_DOORBELL_TO_SDM 0x400 /* Doorbell to SDM */
#define MBOX_DOORBELL_FROM_SDM 0x480 /* Doorbell from SDM */
/* Status and bit information returned by RECONFIG_STATUS */
#define RECONFIG_STATUS_RESPONSE_LEN 6
#define RECONFIG_STATUS_STATE 0
#define RECONFIG_STATUS_PIN_STATUS 2
#define RECONFIG_STATUS_SOFTFUNC_STATUS 3
#define MBOX_CFGSTAT_STATE_IDLE 0x00000000
#define MBOX_CFGSTAT_STATE_CONFIG 0x10000000
#define MBOX_CFGSTAT_STATE_FAILACK 0x08000000
#define MBOX_CFGSTAT_STATE_ERROR_INVALID 0xf0000001
#define MBOX_CFGSTAT_STATE_ERROR_CORRUPT 0xf0000002
#define MBOX_CFGSTAT_STATE_ERROR_AUTH 0xf0000003
#define MBOX_CFGSTAT_STATE_ERROR_CORE_IO 0xf0000004
#define MBOX_CFGSTAT_STATE_ERROR_HARDWARE 0xf0000005
#define MBOX_CFGSTAT_STATE_ERROR_FAKE 0xf0000006
#define MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO 0xf0000007
#define MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR 0xf0000008
#define RCF_SOFTFUNC_STATUS_CONF_DONE BIT(0)
#define RCF_SOFTFUNC_STATUS_INIT_DONE BIT(1)
#define RCF_SOFTFUNC_STATUS_SEU_ERROR BIT(3)
#define RCF_PIN_STATUS_NSTATUS BIT(31)
int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, u8 urgent,
u32 *resp_buf_len, u32 *resp_buf);
int mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg,
u8 urgent, u32 *resp_buf_len, u32 *resp_buf);
int mbox_send_cmd_only(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg);
int mbox_send_cmd_only_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg);
int mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len);
int mbox_rcv_resp_psci(u32 *resp_buf, u32 resp_buf_max_len);
int mbox_init(void);
#ifdef CONFIG_CADENCE_QSPI
int mbox_qspi_close(void);
int mbox_qspi_open(void);
#endif
int mbox_reset_cold(void);
#endif /* _MAILBOX_S10_H_ */
......@@ -27,4 +27,6 @@ unsigned int shared_uart_com_port(const void *blob);
unsigned int uart_com_port(const void *blob);
#endif
void do_bridge_reset(int enable);
#endif /* _MISC_H_ */
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
*
*/
#ifndef _SDRAM_S10_H_
#define _SDRAM_S10_H_
unsigned long sdram_calculate_size(void);
int sdram_mmr_init_full(unsigned int sdr_phy_reg);
int sdram_calibration_full(void);
#define DDR_TWR 15
#define DDR_READ_LATENCY_DELAY 40
#define DDR_ACTIVATE_FAWBANK 0x1
/* ECC HMC registers */
#define DDRIOCTRL 0x8
#define DDRCALSTAT 0xc
#define DRAMADDRWIDTH 0xe0
#define ECCCTRL1 0x100
#define ECCCTRL2 0x104
#define ERRINTEN 0x110
#define INTMODE 0x11c
#define INTSTAT 0x120
#define AUTOWB_CORRADDR 0x138
#define ECC_REG2WRECCDATABUS 0x144
#define ECC_DIAGON 0x150
#define ECC_DECSTAT 0x154
#define HPSINTFCSEL 0x210
#define RSTHANDSHAKECTRL 0x214
#define RSTHANDSHAKESTAT 0x218
#define DDR_HMC_DDRIOCTRL_IOSIZE_MSK 0x00000003
#define DDR_HMC_DDRCALSTAT_CAL_MSK BIT(0)
#define DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK BIT(16)
#define DDR_HMC_ECCCTL_CNT_RST_SET_MSK BIT(8)
#define DDR_HMC_ECCCTL_ECC_EN_SET_MSK BIT(0)
#define DDR_HMC_ECCCTL2_RMW_EN_SET_MSK BIT(8)
#define DDR_HMC_ECCCTL2_AWB_EN_SET_MSK BIT(0)
#define DDR_HMC_ECC_DIAGON_ECCDIAGON_EN_SET_MSK BIT(16)
#define DDR_HMC_ECC_DIAGON_WRDIAGON_EN_SET_MSK BIT(0)
#define DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK BIT(0)
#define DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK BIT(1)
#define DDR_HMC_INTSTAT_SERRPENA_SET_MSK BIT(0)
#define DDR_HMC_INTSTAT_DERRPENA_SET_MSK BIT(1)
#define DDR_HMC_INTSTAT_ADDRMTCFLG_SET_MSK BIT(16)
#define DDR_HMC_INTMODE_INTMODE_SET_MSK BIT(0)
#define DDR_HMC_RSTHANDSHAKE_MASK 0x000000ff
#define DDR_HMC_CORE2SEQ_INT_REQ 0xF
#define DDR_HMC_SEQ2CORE_INT_RESP_MASK BIT(3)
#define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f
/* NOC DDR scheduler */
#define DDR_SCH_ID_COREID 0
#define DDR_SCH_ID_REVID 0x4
#define DDR_SCH_DDRCONF 0x8
#define DDR_SCH_DDRTIMING 0xc
#define DDR_SCH_DDRMODE 0x10
#define DDR_SCH_READ_LATENCY 0x14
#define DDR_SCH_ACTIVATE 0x38
#define DDR_SCH_DEVTODEV 0x3c
#define DDR_SCH_DDR4TIMING 0x40
#define DDR_SCH_DDRTIMING_ACTTOACT_OFF 0
#define DDR_SCH_DDRTIMING_RDTOMISS_OFF 6
#define DDR_SCH_DDRTIMING_WRTOMISS_OFF 12
#define DDR_SCH_DDRTIMING_BURSTLEN_OFF 18
#define DDR_SCH_DDRTIMING_RDTOWR_OFF 21
#define DDR_SCH_DDRTIMING_WRTORD_OFF 26
#define DDR_SCH_DDRTIMING_BWRATIO_OFF 31
#define DDR_SCH_DDRMOD_BWRATIOEXTENDED_OFF 1
#define DDR_SCH_ACTIVATE_RRD_OFF 0
#define DDR_SCH_ACTIVATE_FAW_OFF 4
#define DDR_SCH_ACTIVATE_FAWBANK_OFF 10
#define DDR_SCH_DEVTODEV_BUSRDTORD_OFF 0
#define DDR_SCH_DEVTODEV_BUSRDTOWR_OFF 2
#define DDR_SCH_DEVTODEV_BUSWRTORD_OFF 4
/* HMC MMR IO48 registers */
#define CTRLCFG0 0x28
#define CTRLCFG1 0x2c
#define DRAMTIMING0 0x50
#define CALTIMING0 0x7c
#define CALTIMING1 0x80
#define CALTIMING2 0x84
#define CALTIMING3 0x88
#define CALTIMING4 0x8c
#define CALTIMING9 0xa0
#define DRAMADDRW 0xa8
#define DRAMSTS 0xec
#define NIOSRESERVED0 0x110
#define NIOSRESERVED1 0x114
#define NIOSRESERVED2 0x118
#define DRAMADDRW_CFG_COL_ADDR_WIDTH(x) \
(((x) >> 0) & 0x1F)
#define DRAMADDRW_CFG_ROW_ADDR_WIDTH(x) \
(((x) >> 5) & 0x1F)
#define DRAMADDRW_CFG_BANK_ADDR_WIDTH(x) \
(((x) >> 10) & 0xF)
#define DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(x) \
(((x) >> 14) & 0x3)
#define DRAMADDRW_CFG_CS_ADDR_WIDTH(x) \
(((x) >> 16) & 0x7)
#define CTRLCFG0_CFG_MEMTYPE(x) \
(((x) >> 0) & 0xF)
#define CTRLCFG0_CFG_DIMM_TYPE(x) \
(((x) >> 4) & 0x7)
#define CTRLCFG0_CFG_AC_POS(x) \
(((x) >> 7) & 0x3)
#define CTRLCFG0_CFG_CTRL_BURST_LEN(x) \
(((x) >> 9) & 0x1F)
#define CTRLCFG1_CFG_DBC3_BURST_LEN(x) \
(((x) >> 0) & 0x1F)
#define CTRLCFG1_CFG_ADDR_ORDER(x) \
(((x) >> 5) & 0x3)
#define CTRLCFG1_CFG_CTRL_EN_ECC(x) \
(((x) >> 7) & 0x1)
#define DRAMTIMING0_CFG_TCL(x) \
(((x) >> 0) & 0x7F)
#define CALTIMING0_CFG_ACT_TO_RDWR(x) \
(((x) >> 0) & 0x3F)
#define CALTIMING0_CFG_ACT_TO_PCH(x) \
(((x) >> 6) & 0x3F)
#define CALTIMING0_CFG_ACT_TO_ACT(x) \
(((x) >> 12) & 0x3F)
#define CALTIMING0_CFG_ACT_TO_ACT_DB(x) \
(((x) >> 18) & 0x3F)
#define CALTIMING1_CFG_RD_TO_RD(x) \
(((x) >> 0) & 0x3F)
#define CALTIMING1_CFG_RD_TO_RD_DC(x) \
(((x) >> 6) & 0x3F)
#define CALTIMING1_CFG_RD_TO_RD_DB(x) \
(((x) >> 12) & 0x3F)
#define CALTIMING1_CFG_RD_TO_WR(x) \
(((x) >> 18) & 0x3F)
#define CALTIMING1_CFG_RD_TO_WR_DC(x) \
(((x) >> 24) & 0x3F)
#define CALTIMING2_CFG_RD_TO_WR_DB(x) \
(((x) >> 0) & 0x3F)
#define CALTIMING2_CFG_RD_TO_WR_PCH(x) \
(((x) >> 6) & 0x3F)
#define CALTIMING2_CFG_RD_AP_TO_VALID(x) \
(((x) >> 12) & 0x3F)
#define CALTIMING2_CFG_WR_TO_WR(x) \
(((x) >> 18) & 0x3F)
#define CALTIMING2_CFG_WR_TO_WR_DC(x) \
(((x) >> 24) & 0x3F)
#define CALTIMING3_CFG_WR_TO_WR_DB(x) \
(((x) >> 0) & 0x3F)
#define CALTIMING3_CFG_WR_TO_RD(x) \
(((x) >> 6) & 0x3F)
#define CALTIMING3_CFG_WR_TO_RD_DC(x) \
(((x) >> 12) & 0x3F)
#define CALTIMING3_CFG_WR_TO_RD_DB(x) \
(((x) >> 18) & 0x3F)
#define CALTIMING3_CFG_WR_TO_PCH(x) \
(((x) >> 24) & 0x3F)
#define CALTIMING4_CFG_WR_AP_TO_VALID(x) \
(((x) >> 0) & 0x3F)
#define CALTIMING4_CFG_PCH_TO_VALID(x) \
(((x) >> 6) & 0x3F)
#define CALTIMING4_CFG_PCH_ALL_TO_VALID(x) \
(((x) >> 12) & 0x3F)
#define CALTIMING4_CFG_ARF_TO_VALID(x) \
(((x) >> 18) & 0xFF)
#define CALTIMING4_CFG_PDN_TO_VALID(x) \
(((x) >> 26) & 0x3F)
#define CALTIMING9_CFG_4_ACT_TO_ACT(x) \
(((x) >> 0) & 0xFF)
#endif /* _SDRAM_S10_H_ */
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
*
*/
#include <common.h>
#include <wait_bit.h>
#include <asm/io.h>
#include <asm/arch/mailbox_s10.h>
#include <asm/arch/system_manager.h>
#include <asm/secure.h>