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  • Uwe Kleine-König's avatar
    watchdog: omap: assert the counter being stopped before reprogramming · 530c11d4
    Uwe Kleine-König authored
    The omap watchdog has the annoying behaviour that writes to most
    registers don't have any effect when the watchdog is already running.
    Quoting the AM335x reference manual:
    
    	To modify the timer counter value (the WDT_WCRR register),
    	prescaler ratio (the WDT_WCLR[4:2] PTV bit field), delay
    	configuration value (the WDT_WDLY[31:0] DLY_VALUE bit field), or
    	the load value (the WDT_WLDR[31:0] TIMER_LOAD bit field), the
    	watchdog timer must be disabled by using the start/stop sequence
    	(the WDT_WSPR register).
    
    Currently the timer is stopped in the .probe callback but still there
    are possibilities that yield to a situation where omap_wdt_start is
    entered with the timer running (e.g. when /dev/watchdog is closed
    without stopping and then reopened). In such a case programming the
    timeout silently fails!
    
    To circumvent this stop the timer before reprogramming.
    
    Assuming one of the first things the watchdog user does is setting the
    timeout explicitly nothing too bad should happen because this explicit
    setting works fine.
    
    Fixes: 7768a13c
    
     ("[PATCH] OMAP: Add Watchdog driver support")
    Signed-off-by: default avatarUwe Kleine-König <u.kleine-koenig@pengutronix.de>
    Reviewed-by: default avatarGuenter Roeck <linux@roeck-us.net>
    Signed-off-by: default avatarWim Van Sebroeck <wim@iguana.be>
    530c11d4