• Suzuki K Poulose's avatar
    arm64: Introduce raw_{d,i}cache_line_size · 072f0a63
    Suzuki K Poulose authored
    On systems with mismatched i/d cache min line sizes, we need to use
    the smallest size possible across all CPUs. This will be done by fetching
    the system wide safe value from CPU feature infrastructure.
    However the some special users(e.g kexec, hibernate) would need the line
    size on the CPU (rather than the system wide), when either the system
    wide feature may not be accessible or it is guranteed that the caller
    executes with a gurantee of no migration.
    Provide another helper which will fetch cache line size on the current CPU.
    
    Cc: Mark Rutland <mark.rutland@arm.com>
    Cc: Will Deacon <will.deacon@arm.com>
    Cc: Catalin Marinas <catalin.marinas@arm.com>
    Acked-by: default avatarJames Morse <james.morse@arm.com>
    Reviewed-by: default avatarGeoff Levand <geoff@infradead.org>
    Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
    Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
    072f0a63