Xilinx changes for v2024.01-rc1 ceva sata: - Use generic_phy_valid() helper clk: - Dont return error when assigned-clocks is empty or missing dm: - Support reading a single indexed u64 value - Add support for reading bootscript address/flash address from DT cmd: - Fix flash_is_unlocked API fpga: - Define fpga_load() for debug build global: - U-Boot project name cleanup (next2) net: - zynq_gem: Use generic_phy_valid() helper - axienet: Convert to ofnode functions - gmii2rgmii: Read bridge address from DT pytest: - skip tpm2_startup when env__tpm_device_test_skip=True spi-nor: - Add mx25u25635f support - zynqmp_qspi: Tune cache behavior trace: - Fix flyrecord alignment issue xilinx: - Move scriptaddr to DT as bootscr-address - Pick script_offset_f/script_size_f from DT as bootscr-flash-offset/size - Do not generate distro boot variables if disabled versal: - Extend memory ranges to cover HBM - Enable TPM, sha1sum and KASLRSEED - Fix distroboot prioritization in connection to available devices - Clean mini targets bootcommand - Fix clock driver versal-net: - Enable TPM, sha1sum and KASLRSEED - Fix distroboot prioritization in connection to available devices zynqmp; - Allow AES to run from SPL - Enable CMD_KASLRSEED - Add proper dependencies for USB and remove ZYNQMP_USB - Fix user si570 default frequency for zcu* boards - Cover SOM rev2 revision - Various DT changes - Add firmware and pinctrl support for tristate configuration (high impedance/output enable) - Add output-enable pins to SOMs - Fix distroboot prioritization in connection to available devices - Read bootscript address/flash address from DT - Fix pcap_prog address